Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-10-23
2004-12-21
Yoha, Connie C. (Department: 2818)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C710S001000, C710S007000, C710S020000, C710S022000
Reexamination Certificate
active
06833728
ABSTRACT:
TECHNICAL FIELD
This invention relates to an electronic circuit having an interface port.
BACKGROUND
Integrated circuits send output signals and receive input signals through input/output pins. To prevent input signals from interfering with output signals, an input pin may be dedicated for receiving input signals, and an output pin may be dedicated for transmitting output signals. A single bi-directional pin can also be used to allow input and output signals to pass through the pin at different times. Use of bi-directional pins reduces the number of pins on the integrated circuit package and therefore decreases its size. However, conventional bi-directional pins reduce the rate at which signals can be received and transmitted because only one signal can appear at the bi-directional pin at any given instant to prevent signal interference.
SUMMARY
In general, in one aspect, the invention is directed to an apparatus having an interface port for simultaneously transmitting and receiving input and output signals. The apparatus includes a first circuit for generating the output signal and a second circuit having first and second terminals with the first terminal coupled to the first circuit and the second terminal coupled to the interface port. A signal level at the first terminal represents a first combination of the input and output signals, and a signal level at the second terminal represents a second combination of the input and output signals. A third circuit is coupled to the first and second terminals of the second circuit for determining the input signal based on the signal levels at the first and second terminals. This aspect may include one or more of the following features.
The third circuit processes the signal levels at the first and second terminals to generate a signal corresponding to the input signal. The third circuit multiplies the signal level at the first terminal by a first constant to generate a first number, and multiplies the signal level at the second terminal by a second constant to generate a second number. The difference between the second and the first numbers corresponds to the input signal. When the interface port is coupled to a transmission line having an impedance of Z, and the second circuit has a resistance of Ra, the ratio between the first constant and the second constant is selected to be approximately equal to Z/(Z+Ra). When a resistance of Rc exits between the interface port and the transmission line, a resistance of Rb exists between the interface port and the electric ground, the ratio between the first constant and the second constant is selected to be approximately equal to Rb*(Z+Rc)/(Rb* (Z+Rc)+Ra*(Rb+Rc+Z)).
In general, in another aspect, the invention is directed to a system including a transmission line having first end and second ends with signals sent bi-directionally on the transmission line simultaneously. The system includes a first driver for generating a first output signal, and a first bridge having a first terminal coupled to the first driver and a second terminal coupled to the first end of the transmission line. The system further includes a second driver for generating a second output signal, and a second bridge having a first terminal coupled to the second driver and a second terminal coupled to the second end of the transmission line. The system further includes a first arithmetic unit for processing the signal levels at the first and second terminals of the first bridge to generate a first computed signal that corresponds to the second output signal. The system further includes a second arithmetic unit for processing the signal levels at the first and second terminals of the second bridge to generate a second computed signal that corresponds to the first output signal.
In general, in another aspect, the invention is directed to a memory chip that has an interface pin for simultaneously reading in write data to the memory chip and sending out read data from the memory chip. The memory chip includes a driver for generating the read data, and an internal impedance/resistance having a first terminal coupled to the driver and a second terminal coupled to the interface pin. The memory chip further includes an arithmetic unit for processing signal levels at the first and second terminals of the internal impedance/resistance and for generating a signal corresponding to the write data.
In general, in another aspect, the invention is directed to a system that includes a data bus, a processor, and a memory. The data bus has a first end and a second end. The processor has a first arithmetic unit and a first interface port coupled to the first end of the data bus. The memory has a second arithmetic unit and a second interface port coupled to the second end of the data bus. The processor sends a write signal via the data bus to the memory at the same time that the memory sends a read signal via the data bus to the processor. The first arithmetic unit processes combinations of the write and read signals to generate a first computed signal corresponding to the read signal. The second arithmetic unit processes combinations of the read and write signals to generate a second computed signal corresponding to the write signal.
In general, in another aspect, the invention is directed to a system that includes a data bus having a first end and a second end, a first device, and a second device. The first device has a first driver for generating a first output signal, a first bridge having a first terminal for coupling to the first driver and a second terminal for coupling to the first end of the data bus, and a first arithmetic unit. The second device has a second driver for generating a second output signal, a second bridge having a first terminal for coupling to the second driver and a second terminal for coupling to the second end of the data bus, and a second arithmetic unit. The first arithmetic unit processes signal levels of the first and second terminals of the first bridge to generate a first computed signal that corresponds to the second output signal, and the second arithmetic unit processes signal levels of the first and second terminals of the second bridge to generate a second computed signal that corresponds to the first output signal.
Implementations of the invention may include one or more of the following features. The first device may be a computer. The second device may be an input/output device. The second device may be a disk drive.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
REFERENCES:
patent: 4245301 (1981-01-01), Rokutanda et al.
patent: 5557236 (1996-09-01), Monti
patent: 5721838 (1998-02-01), Takahashi et al.
Fish & Richardson P.C.
Infineon - Technologies AG
Yoha Connie C.
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