Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
2000-08-23
2004-11-02
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S045000, C710S057000, C370S230000, C370S232000, C370S364000, C370S468000
Reexamination Certificate
active
06813654
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-238775 (publication number 2001-067309), filed Aug. 25, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a data processing apparatus and a data transfer control method thereof and, more particularly, to a data processing apparatus for processing various kinds of data, such as audio/video data, other data and programs, and a data transfer control method thereof.
Recently, as the computer technology is advancing, various types of digital information device, such as multimedia-handling personal computers, set-top boxes, digital TVs and game machines, have been developed. There has been a demand for a capability to handle various kinds of media, such as broadcasting media, communication media and storage media, in digital information devices of this type.
Accordingly, people are demanding that personal computers should be provided with a function of processing AV (Audio/Video) stream data that needs real-time processing in addition to functions of processing ordinary programs. For consumer AV machines, such as set-top boxes, digital TVs and game machines, there has been a demand for a function of processing computer data, i.e., data other than A/V stream data, and programs, in order to adapt the machines to software-controlled interactive title playback or the like.
Because the bus architecture of conventional computers handle an AV stream and computer data as the same type, however, they are inadequate to feed AV streams that demand highly real-time processing. When a traffic of computer data becomes suddenly heavy while AV stream data and computer data are flowing on the bus at the same time (e.g., at the time of printing or accessing to a file), the AV stream data brings about a significant transfer delay. The reason is as follows. AV stream data and computer data are not distinguished from each other when they are transferred on the bus and thus it is not possible to perform a process of causing AV stream data, which needs real-time processing, flow first by priority.
Further, since the architectures of conventional computer machines have a difficulty in guaranteeing the latency of data transfer, they require that a huge buffer for guaranteeing the latency be provided in an AV device or the like which is to be connected to the bus. In a case of handling streams of a variable bit rate, such as DVD titles, it was necessary to install a large buffer so that the buffer on a reception-side device would not overflow even at the maximum transfer rate. This requirement is a big factor to increase the cost. In order to multi-cast AV stream data to a plurality of devices, a huge buffer has to be provided at every device on the receiver side. This increases the cost greatly.
Furthermore, if priority is given only to the transfer of AV stream data, when an event which needs fast processing occurs, a process for that event may be delayed.
Conventional AV machines physically accomplish peer-to-peer connection of devices that handle AV streams by connecting a plurality of devices in the processing order of the AV streams. Therefore, in conventional AV machine, AV streams are not basically input to a CPU. The recent appearance of media (hyper media), which has AV streams and interactive commands integrated, demands that a CPU should process streams. This makes the present physical peer-to-peer connection of devices difficult, and studies on bus connection have started.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a data processing apparatus capable of an efficient multi-cast transfer of stream data through a bus without providing any huge buffer, and a data transfer control method of the data processing apparatus.
To attain the above object, a data processing apparatus according to the present invention comprises a bus for which a band-guaranteed cycle capable of transferring stream data in real time by assigning a predetermined reserved band for each cycle time is defined, a plurality of nodes connected to the bus and capable of transmitting/receiving stream data using the band-guaranteed cycle, means for executing a multi-cast transfer of stream data from a sender node to a plurality of receiver nodes using the band-guaranteed cycle, and means for detecting that any of the plurality of receiver nodes drives a signal line in the bus, which indicates a completion of a data transfer cycle; and means for stopping the multi-cast transfer upon detection of the detecting means.
In the above arrangement, too, the problem of a drive conflict among signals of the plural receiver nodes can be resolved without decreasing the bus use efficiency.
According to the system of the present embodiment described above, the use of the bus in which the band-guaranteed cycle is defined as a transfer mode allows the band of stream data requiring a high degree of real time to be guaranteed. Usually data transfer cannot be intermitted during the band-guaranteed cycle; however, in the present invention, the transmission of stream data from the sender node can be stopped under the control of the receiver node, even during the band-guaranteed cycle.
The multi-cast transfer using the band-guaranteed cycle can be stopped even in response to an instruction from any receiver node. The provision of this scheme of stopping the multi-cast transfer of stream data under the control of the receiver node can prevent the buffer from overflowing even when such overflowing is likely to occur at any receiver node for the multi-cast due to a delay in the stream processing and reception of a variable bit rate stream. It is therefore possible to efficiently execute the multi-cast transfer of stream data through the bus only with the least required buffer.
When the signal line for indicating the completion of a data transfer cycle is so formed that it can be driven by any receiver node, if a drive conflict occurs among signals of the plural receiver nodes, the signal line is set in an unstable state between low and high levels, thus causing the device to malfunction. Therefore, a pull-up or pull-down load circuit is connected to the signal line, and it is preferable that an operation for driving the signal line into the active state be performed through an output buffer provided at each receiver node. The above problem can thus be resolved. Since, in this case, a shift of the signal line from the active state to the inactive state is performed by the load circuit, a relatively long time is required and accordingly an operator therefore has to wait a long time until the transfer of data is started through the multimedia bus, and it is likely that bus use efficiency will be reduced. It is therefore preferable to further comprise acceleration means for driving the signal line into an inactive state for a predetermined time period after the signal line is driven into the active state by the receiver node in order to accelerate a shift of the signal line to the inactive state. If the acceleration means is provided at the manager node to allow it to drive the signal line into the inactive state, the operation can be increased further in reliability.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
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Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Gaffin Jeffrey
Kabushiki Kaisha Toshiba
Patel Niketa I.
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