Electric heating – Metal heating – By arc
Reexamination Certificate
2003-07-24
2004-08-24
Hoang, Tu (Department: 3742)
Electric heating
Metal heating
By arc
C219S121440, C219S121580, C219S121590, C373S018000
Reexamination Certificate
active
06781086
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of removing photoresist. More particularly, the present invention relates to an ashing process for removing photoresist from a wafer.
2. Description of the Related Art
Usually, a semiconductor chip is manufactured from a pure silicon wafer by repeatedly performing unit processes on the wafer, such as photolithography, etching, ashing, ion diffusion, and film deposition processes.
Photolithography comprises a step of spin-coating the wafer with a photoresist (material capable of facilitating a photochemical reaction), a step of exposing the wafer to radiation (such as ultraviolet light) directed through a reticle bearing a pattern corresponding to that of a circuit pattern such that the pattern of the reticle is replicated in the photoresist, and a step of developing the photoresist to pattern the photoresist. After the photoresist is patterned, the wafer is etched using the photoresist pattern as a mask so that the circuit pattern is produced on the wafer. Then the photoresist remaining on the wafer is removed by ashing.
Conventional ashing apparatus include wet ashing apparatus for removing the photoresist using chemicals and dry ashing apparatus for removing the photoresist using plasma and O
3
. Recently, dry ashing apparatus for removing the photoresist using plasma have been mainly used in the industry. Examples of such dry ashing apparatus are disclosed in U.S. Pat. No. 5,226,056 and U.S. Pat. No. 5,228,052.
The conventional dry ashing apparatus disclosed in these patents comprise a process chamber in which the ashing process is performed, a wafer stage for supporting the wafer to be ashed, wafer setting pins disposed on the wafer stage for positioning the wafer relative to the wafer stage, and a heater installed within the wafer stage for heating the positioned wafer to a desired temperature.
A processed wafer is transferred by a transfer apparatus into the process chamber of the ashing apparatus. The wafer setting pins are raised a desired distance above the wafer stage to receive the wafer. The wafer setting pins are then lowered to a position at which the wafer is positioned on the upper surface of the wafer stage.
Once the wafer is positioned on the upper surface of the wafer stage, the wafer is heated by the heater to a desired temperature. Subsequently, process gases are supplied into the process chamber and the gases are excited by supplying power thereto in order to produce plasma. The plasma reacts with the upper surface of the wafer positioned on the wafer stage. Thus, the patterned photoresist situated at the upper surface of the wafer is removed, i.e., is ashed.
However, the conventional plasma ashing apparatus cannot remove the photoresist from all of the surfaces (front, side, and rear) of the wafer that are coated with the photoresist during the photolithography process, because the wafer rests on the upper surface of the wafer stage during the ashing process. That is, photoresist is only removed from the upper surface of the wafer by the plasma.
Accordingly, a pin-up ashing process has been proposed for removing the photoresist from the side surface and rear surface of the wafer. The conventional pin-up ashing process comprises ashing the wafer at a desired height from the wafer stage after the photoresist has been removed from the upper surface of the wafer by ashing. Such a pin-up ashing process allows all of the photoresist to be removed from the wafer, including that on the side and rear surfaces of the wafer. However, if the conventional pin-up ashing process requires a large amount of time for removing the photoresist separately from the upper surface, and from the side and rear surfaces of the wafer. Accordingly, the conventional pin-up ashing process lowers the productivity of the overall manufacturing process.
The subsequent processes, such as a diffusion process, may take place at a temperature greater than 800° C. If the pin-up ashing process is omitted to save time, the photoresist remains on the side and rear surfaces of the wafer during the subsequent high-temperature process. In this case, the photoresist is oxidized. Oxidation of the photoresist may produce defects in the resultant semiconductor device.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of efficiently removing photoresist from all surfaces of a wafer.
According to one aspect of the present invention, the method comprises step for transferring a wafer coated with a photoresist into a process chamber, positioning the wafer on the upper surface of the wafer stage and heating the wafer on the wafer stage to a temperature of 210° C. to 230° C. using the heater disposed within the stage, raising the heated wafer a predetermined desired above the upper surface of the wafer, and only ashing the photoresist from the wafer with plasma once the wafer has been raised above the upper surface of the wafer stage.
Preferably, the wafer is manipulated within the process chamber by one or more setting pins extending through the wafer stage. The setting pins are first raised from a wafer stage inside the process chamber to receive the wafer. The wafer setting pins are then lowered to set the wafer down on the upper surface of the wafer stage where the wafer is heated. Finally, the wafer setting pins are raised to position the wafer above the upper surface of the wafer stage in preparation for the ashing process. The distance by which the wafer is spaced from the upper surface of the wafer stage during the only ashing process is preferably between 9 mm to 11 mm, whereby the wafer remains at a temperature of 210° C. to 230° C.
REFERENCES:
patent: 4626315 (1986-12-01), Kitamoto et al.
patent: 4717806 (1988-01-01), Battey et al.
patent: 5226056 (1993-07-01), Kikuchi et al.
patent: 5228052 (1993-07-01), Kikuchi et al.
patent: 5445710 (1995-08-01), Hori et al.
patent: 6259072 (2001-07-01), Kinnard et al.
patent: 6326574 (2001-12-01), Huang et al.
Hoang Tu
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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