Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-04-11
2004-06-15
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S227000, C365S230060
Reexamination Certificate
active
06751143
ABSTRACT:
TECHNICAL FIELD
This invention relates to dynamic random access memory devices, and, more particularly, to a method and system for allowing a memory device to be quickly and easily switched into and out of a low power, half density, operating mode.
BACKGROUND OF THE INVENTION
As the use of electronic devices, such as personal computers, continue to increase, it is becoming ever more important to make such devices portable. The usefulness of portable electronic devices, such as notebook computers, is the limited by the limited length of time batteries are capable of powering the device before needing to be recharged. This problem has been addressed by attempts to increase battery life and attempts to reduce the rate at which such electronic devices consume power.
Various techniques have been used to reduce power consumption in electronic devices, the nature of which often depends upon the type of power consuming electronic circuits that are in the device. For example, electronic devices, such a notebook computers, typically include dynamic random access memory (“DRAM”) devices that consume a substantial amount of power. As the data storage capacity and operating speeds of DRAM devices continues to increase, the power consumed by such devices has continued to increase in a corresponding manner.
A variety of operations are performed in DRAM devices, each of which affects the rate at which the DRAM device consumes power. One operation that tends to consume power at a substantial rate is refresh of memory cells in the DRAM device. As is well-known in the art, DRAM memory cells, each of which essentially consists of a capacitor, must be periodically refreshed to retain data stored in the DRAM device. Refresh is typically performed by essentially reading data bits from the memory cells in each row of a memory cell array and then writing those same data bits back to the same cells in the row. This refresh is generally performed on a row-by-row basis at a rate needed to keep charge stored in the memory cells from leaking excessively between refreshes. Since refresh essentially involves reading data bits from and writing data bits to a large number of memory cells refresh tends to be a particularly power-hungry operation. Thus many attempts to reduce power consumption in DRAM devices have focused on reducing the rate at which power is consumed during refresh.
The amount of power consumed by refresh also depends on which of several refresh modes is active. A Self Refresh mode is normally active during periods when data are not being read from or written to the DRAM device. Since portable electronic devices are often inactive for substantial periods of time, the amount of power consumed during Self Refresh can be an important factor in determining how long the electronic device can be used between battery charges.
One technique that has been used to reduce the amount of power consumed by refreshing DRAM memory cells is to vary the refresh rate as a function of temperature. As is well known in the art, the rate at which charge leaks from a DRAM memory cell increases with temperature. The refresh rate must be sufficiently high to ensure that no data is lost at the highest temperature in the specified range of operating temperatures of the DRAM device. Yet, DRAM devices normally operate at a temperature that is substantially lower than their maximum operating temperature. Therefore, DRAM devices are generally refreshed at a rate that is higher than the rate actually needed to prevent data from being lost, and, as a result, unnecessarily consume power. To address this problem, some commercially available DRAM devices allow the user to program a mode register to select a lower maximum operating temperature. The DRAM device then adjusts the refresh rate to correspond to the maximum operating temperature selected by the user.
Although adjusting the refresh rate as a function of temperature does reduce the rate of power consumed by refresh, it nevertheless still allows power to be consumed at a significant rate for several reasons. For example, although the refresh rate may be reduced with reduced maximum operating temperature, the refresh may still result in refreshing a large number of memory cells that are not actually storing data.
Another approach to reducing the rate at which power is consumed by a refresh operation is to refresh less than all of the memory cells in the DRAM device in attempt to refresh only those memory cells needed to store data for a given application. As described in U.S. Pat. No. 5,148,546 to Blodgett, a software program being executed in a computer system containing the DRAM devices is analyzed to determine the data storage requirements for the program. The DRAM device then refreshed only those rows of memory cells that are needed to store data. In another approach, the DRAM device may be operated in a partial array self refresh (“PASR”) mode. In the PASR mode, a mode register is programmed by a user to specify a bank or portion thereof of memory cells that will be used and thus must be refreshed. The remaining memory cells are not used and thus need not be refreshed during at least some refresh modes. Although these techniques for refreshing less than all of the memory cells in a memory device can substantially reduce the rate of power consumption, it can nevertheless require a substantial amount of power to refresh the cells that are to be refreshed.
Still another technique that can be used to reduce the rate of refresh involves operating DRAM devices in a half density mode. A DRAM device that may be operated in a half density mode is described in U.S. Pat. No. 5,781,483 to Shore. In the half density mode, the low order bit of each row address, which normally designates whether the addressed row is even or odd, is ignored, and both the odd row and adjacent even row are addressed for each memory access. In a folded digit line architecture, activating an odd row will couple each memory cell in the row to a respective digit line, and activating an even row will couple each memory cell in the row to a respective complimentary digit line. Thus, for example, writing a “1” to an addressed row and column would result in writing a logic “1” voltage level to the memory cell in the addressed odd row and writing a logic “0” logic level to the memory cell in the addressed even row. Reading from the addressed row and column results in a logic “1” voltage level being applied to the digit line for the addressed column and a logic “0” voltage level being applied to the complimentary digit line for the addressed column. Therefore, in the half density mode, a sense amplifierlifier coupled to the digit line and complimentary digit line for each column receives twice the differential voltage that it normally receives when reading a memory cell at an addressed row and column.
The patent to Shore describes the use of the half density mode for the purpose of allowing the DRAM device to be used despite the presence of defective memory cells. If a memory cell in an addressed row and column is defective, the data bit stored in that memory cell can still be recovered from the other memory cell in the addressed row and column. However, it has been recognized that the half density mode can be used to reduce that rate at which power is consumed during refresh. Although a refresh in the half density mode requires twice as many memory cells to be refreshed for a given amount of stored data, the required refresh rate is less than half the required refresh rate when the DRAM device is operating in the full density mode. The substantially lower refresh rate required in the half density results from the increased differential voltage that is applied to the sense amplifierlifiers in the half density mode, as previously explained. As a result, the memory cells can be allowed to discharge to a greater degree between refreshes without the data bits stored therein being lost. Therefore, storing data in the half density mode can reduce the rate of power consumption during refresh
In conventional DRAM device
Blodgett Greg A.
Morgan Donald M.
Dorsey & Whitney LLP
Elms Richard
Micro)n Technology, Inc.
Nguyen Hien
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