Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-03-29
2004-10-19
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S424000, C438S425000, C438S253000, C438S254000, C438S396000, C438S397000, C257S296000, C257S306000, C257S297000, C257S298000, C257S300000
Reexamination Certificate
active
06806188
ABSTRACT:
CROSS REFERENCES TO RELATED APPLICATIONS
This application claims the benefit under 35 U.S.C. §119 of Korean Patent Application No. 2002-12736, filed on Mar. 9, 2002, the entirety of which is hereby incorporated herein by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of preventing a ring defect, which may occur in an interlayer dielectric layer when forming conductive lines, such as bitlines, and a method of manufacturing the same.
2. Description of the Related Art
As the integration density of semiconductor devices has increased, research has been carried out more vigorously on a multilayered wiring layer technique which enables free and easy design of wiring layers and reduces wiring layer resistance and capacitance.
In the multilayered wiring layer technique, a complex resin material layer, such as a borophosphosilicate glass (BPSG) layer or a phosphosilicate glass (PSG) layer, or a spin on glass (SOG) layer is used as a planarization insulation layer in order to prevent a disconnection of upper wiring layers due to the unevenness of the lower wring layers. Since a SOG layer is weak in processes performed at a high temperature, it is used only in processes for forming upper metal wiring layers. A BPSG layer is used as a planarization layer in processes for forming lower transistors, bitlines, and capacitors.
A BPSG layer is composed of B
2
O
3
, P
2
O
5
, and SiO
2
and is planarized by a predetermined heat treatment, for example, a flow process, after the deposition. The flow process may be performed at a high temperature of no less than 850° C., and the temperature may be varied according to the components of a layer, and the process time and atmosphere of the flow process.
Here, a method of manufacturing a conventional semiconductor device having an interlayer dielectric layer formed of a BPSG layer will be described with reference to FIG.
1
.
Referring to
FIG. 1
, an isolation layer
12
is formed on a semiconductor substrate
10
. Next, a gate oxide layer
14
, a conductive layer
16
, and a capping layer
18
are sequentially deposited on the semiconductor layer
10
and are patterned to form a gate electrode structure (G). Next, a silicon nitride (SiN) layer is deposited on the semiconductor substrate
10
and is etched to form spacers
20
at either sidewall of the gate electrode structure (G) by blanket-anisotropic etching. Next, impurities are implanted into the semiconductor substrate
10
at either side of the gate electrode structure (G), thereby forming a junction region
25
.
Next, in order to alleviate the step difference of the semiconductor substrate
10
caused by the gate electrode structure (G), a BPSG layer
30
is deposited on the semiconductor substrate
10
and is heat-treated at a predetermined temperature to be flowed. Next, an interlayer dielectric layer
32
is deposited on the flowed BPSG layer
30
. The interlayer dielectric layer
32
is introduced to help the BPSG layer
30
to more strongly stick to conductive lines to be formed later.
Next, the inter layer dielectric layer
32
and the BPSG layer
30
are etched to expose the junction region
25
, thereby forming a contact hole. Since the BPSG layer
30
has a higher etching rate than the interlayer dielectric layer
32
, the BPSG layer
30
is etched much more than the interlayer dielectric layer
32
so that the sidewalls of the contact hole are formed as a bow shape, which is called a bowing phenomenon. In
FIG. 1
, “b” represents the portion of the interlayer dielectric layer, at which the bowing phenomenon occurs.
Next, contact spacers
35
are formed at the sidewalls of the contact hole. Next, the surface of the exposed junction region
25
is cleaned, and then a bitline
40
is formed to contact the exposed junction region
25
.
However, since the conventional semiconductor device described above has the contact hole whose sidewalls are formed as a bow shape, the widths of the upper and lower portions of each of the contact spacers
35
are relatively narrow. In addition, if a cleaning process is performed before the formation of the bitline
40
, a thickness of the interlayer dielectric layer
32
and a portion of the contact spacers
35
is washed away so that the interfacial surface between the BPSG layer
30
and the interlayer dielectric layer
32
, and the interfacial surface between the BPSG layer
30
and the junction region
25
are exposed. Accordingly, a cleaning solution infiltrates into the interfacial surfaces and sweeps the BPSG layer
30
at the interfacial surfaces, thereby forming empty spaces in the BPSG layer
30
.
As a result, as shown in
FIG. 1
, in the formation of the bitline
40
, the conductive material of the bitline
40
is deposited in empty spaces in the BPSG layer
30
so that a ring defect
45
is generated in the BPSG layer
30
.
The ring defect
45
may acts a path of leakage current and may cause a short circuit between the gate electrode structure (G, a wordline) and the bitline
40
.
SUMMARY OF THE INVENTION
To solve the above-described problems, it is a first object of the present invention to provide a semiconductor device that is capable of preventing a short circuit from occurring between a wordline and a bitline.
It is a second object of the present invention to provide a semiconductor device which is capable of preventing a ring defect from occurring around a bitline contact area.
It is a third object of the present invention to provide a method of manufacturing the semiconductor device.
Accordingly, to achieve the first and second objects, there is provided a semiconductor device according to a first aspect of the present invention. The semiconductor device includes a semiconductor substrate having a junction region, a planarization layer having a first contact hole portion through which the junction region is exposed, an interlayer dielectric layer formed on the planarization layer and having a second contact hole portion extended from the first contact hole portion, and contact spacers formed at the sidewalls of the first and second contact hole portions. Here, the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate.
To achieve the first and second objects, there is provided a semiconductor device according to a second aspect of the present invention. The semiconductor device includes a semiconductor substrate having a junction region, a planarization layer having a first contact hole portion, through which the junction region is exposed, an interlayer dielectric layer formed on the planarization layer and having a second contact hole portion extended from the first contact hole portion, and contact spacers formed at the sidewalls of the first and second contact hole portions. Here, the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate, the interlayer dielectric layer has a slower etching rate than the planarization layer in an etchant used to form the first and second contact hole portions, and the contact spacers are formed of a material having a slower etching rate than the interlayer dielectric layer and the planarization layer in a cleaning solution.
Preferably, the upper edge of each of the contact spacers is located higher than the upper surface of one portion of the interlayer dielectric layer having a smaller thickness than the other portions of the interlayer dielectric layer.
The junction region includes a groove, through which the interface between the planarization layer and the semiconductor substrate is exposed.
Preferably, the width of the portion of the junction region exposed between the contact spacers is smal
Anya Igwe U.
Smith Matthew
Volentine Francos & Whitt PLLC
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