Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2004-01-12
2004-11-30
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S100000, C711S102000, C711S154000, C365S189011
Reexamination Certificate
active
06826649
ABSTRACT:
TECHNICAL FIELD
The present invention relates to multistate memory devices, and more specifically, to an apparatus and method for reducing the number of programming cycles needed to program a given field of data into the memory cells of a multistate memory system.
BACKGROUND OF THE INVENTION
In conventional single-bit per cell memory devices, the memory cell assumes one of two information storage states, either an “on” state or an “off” state. The binary condition of “on” or “off” defines one bit of information. As a result, a memory device capable of storing n-bits of data requires (n) separate memory cells.
Increasing the number of bits which can be stored using single-bit per cell memory devices depends upon increasing the number of memory cells on a one-for-one basis with the number of bits of data to be stored. Methods for increasing the number of memory bits stored in a memory device composed of single-bit capacity cells have relied upon techniques such as manufacturing larger die which contain more memory cells, or using improved photolithography techniques to build smaller memory cells. Reducing the size of a memory cell allows more cells to be placed on a given area of a single die.
An alternative to single-bit per cell designs is the storage of multiple-bits of data in a single memory cell. One type of memory in which this approach has been followed is an electrically erasable and programmable device known as a flash memory cell. In flash cells, programming is carried out by applying appropriate voltages to the source, drain, and control gate of the device for an appropriate time period. This causes electrons to tunnel or be injected from a channel region to a floating gate. The amount of charge residing on the floating gate determines the voltage required on the control gate in order to cause the device to conduct current between the source and drain regions. This voltage is termed the threshold voltage, V
th
, of the cell. Conduction represents an “on” or erased state of the device and corresponds to a logic value of one. An “off” or programmed state is one in which current is not conducted between the source and drain regions and corresponds to a logic value of zero. By is setting the threshold voltage of the cell to an appropriate value, the cell can be made to either conduct or not conduct current for a given set of applied voltages. Thus, by determining whether a cell conducts current at a given set of applied voltages, the state of the cell (programmed or erased) can be found.
A multi-bit or multistate flash memory cell is produced by creating multiple, distinct threshold voltage levels within the device. Each distinct threshold voltage corresponds to a set of data bits. This allows multiple bits of binary data to be stored within the same memory cell. When reading the state of the memory cell, each cell has a binary decoded value corresponding to a value dependant upon the conduction of the cell at its present threshold voltage level. The threshold voltage level for which the cell compares to a sense amplifier having a preselected input value indicates the bit set representing the data programmed into the cell. Proper data storage requires that the multiple threshold voltage levels of a multistate memory cell be separated from each other by a sufficient amount so that a level of a cell can be programmed or erased in an unambiguous manner. The relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells.
In programming a multistate memory cell, the objective is to apply a programming voltage over a proper time period to store enough charge in the floating gate to move the threshold voltage to a desired level. This level represents a state of the cell corresponding to an encoding of the data which is to be programmed into the cell. However, dividing of the threshold voltage range for a two state (one bit) cell into multiple threshold voltage levels reduces the margin (threshold voltage difference) between levels. This necessitates tighter system design tolerances and reduced programming operation noise margins so that adjacent levels can be differentiated and programming errors reduced. However, the tightening of the programming and read operation threshold voltage windows has led to slower programming procedures and introduced another potential source of memory system errors.
U.S. Pat. No. 5,043,940, entitled “Flash EEPROM Memory Systems Having Multistate Storage Cells”, issued Aug. 27, 1991, describes a method of programming a multistate memory cell in which an iterative read-compare-program cycle is executed. During the cycle, the data intended to be programmed into a memory cell is input to a comparator, along with the outputs from a set of sense amplifiers (each having a different reference voltage) connected to the cell. The output of the sense amplifiers indicates the threshold voltage level to which the cell is programmed. If the programmed threshold voltage level corresponds to the encoded representation of the intended data, then the cell is in the correct state.
If the intended data doesn't correspond to the programmed threshold voltage level, then a programming control circuit is activated. A single, short duration programming pulse is then applied to the cell, followed by another read operation using the sense amplifiers. This cycle is repeated until the data comparison operation indicates a correct threshold voltage level, or until the maximum number of programming pulses has been applied.
U.S. Pat. No. 5,394,362, entitled “Electrically Alterable Non-volatile Memory with N-bits per Memory Cell”, issued Feb. 28, 1995, describes a similar method of programming a multistate memory cell. An iterative cycle of determining the threshold voltage level of a cell, using the threshold voltage level to determine the data contained in the cell, comparing the data programmed into the cell to data intended to be programmed, and then generating a programming pulse to alter the cell's threshold voltage level is performed. This cycle is repeated using the same period and amplitude for the programming pulse during each cycle, until the sense amplifiers indicate that the cell has been properly programmed.
Although both of the described methods for programming a multistate memory cell are capable of performing the desired function, they do so in an inefficient manner. This is because they implement the programming operation for every data field by causing the threshold voltage level to incrementally increase from a base value (the erased state level) until it reaches a desired value. This process can result in an increase in the number of programming states which must be traversed, programming time, and power consumption compared to a system which is capable of programming the memory cells in a manner which reduces the number of higher programming states used to program a given field of data.
What is desired is an apparatus and method for programming a multistate memory cell which reduces the number of higher programming states used to program a given field of data compared to presently used programming methods.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for reducing the number of programming states (threshold voltage levels) required to be traversed when programming a multistate memory cell with a given set of data. This is accomplished by reducing the number of data bits in the higher programming states, thereby reducing programming time, memory system power consumption, and programming errors during the programming of a specified data field. In addition, by reducing the number of programming pulses used, the gate and drain disturb of the memory cells is significantly reduced. This provides the memory system with better long term reliability.
The invention first determines the average programming state (corresponding to an average threshold voltage level) for a given field of data which is to be programmed i
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Thai Tuan V.
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