Semiconductor device and operation method thereof

Details Semiconductor device and operation method thereof Semiconductor device and operation method thereof

2002-10-24

2004-10-19

Abraham, Fetsum (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S319000

Reexamination Certificate

active

06806525

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and an operation thereof, and more particularly to a semiconductor device including a non-volatile memory and an operation thereof.
2. Description of the Related Art
NAND type EEPROMs (electrically erasable programmable read only memory) are popular as semiconductor devices which include electrically programmable and erasable non-volatile memories.
FIG. 19
to
FIG. 23
of the accompanying drawings show a structure of such a NAND type EEPROM, and
FIG. 24
shows a circuit configuration of the NAND type EEPROM.
In the NAND type EEPROM, a memory array
100
is constituted by a plurality of memory cell units
101
arranged in the shape of a matrix. Each memory cell unit
101
includes eight memory cells
102
which are connected in series in a row. Generally speaking, the memory cell
102
can store 1-bit data while the memory cell unit
101
can store 1-byte data.
Referring to
FIG. 21
to
FIG. 23
, the NAND type EEPROM is provided on a main surface of a semiconductor substrate
110
(i.e. a semiconductor chip), which is made of a silicon single crystal substrate. A plurality of memory cells
102
are positioned on the main surface (a well region, not shown) of the semiconductor substrate
110
. The memory cells
102
are surrounded by an element isolate insulating film
111
at a gate width regulating area.
Each memory cell
102
includes: a channel forming region (the semiconductor substrate
110
or the well region); a first gate insulating film
121
; a floating gate electrode (charge storing section)
122
on the first gate insulating film
121
; a second gate insulating film
123
on the floating gate electrode
122
; a control gate electrode
124
on the second gate insulating film
123
; and a pair of semiconductor regions
125
functioning as source and drain regions. In other words, each memory cell
102
is constituted by an n-channel conductivity type field effect transistor including the floating gate electrode
122
. In the memory cell unit
101
, the semiconductor regions
125
, i.e. a source or drain region, of one memory cell
102
in a row are integral with semiconductor regions
125
of another memory cell
102
which is adjacent in the same row. Referring to FIG.
19
and
FIG. 22
, the control gate electrode
124
of one memory cell
102
in a column is integral with a control gate electrode
124
of another memory cell
102
which is adjacent in the same column, thereby constituting a word line
124
WL extending in the column and the row.
A cell selecting transistor
105
is provided for the memory cells
102
at one end of the memory cell unit
101
(i.e., at the upper part in
FIG. 19
, and at the left side in FIG.
23
). Further, a cell selecting transistor
106
is provided for the memory cell at the other end of the memory cell unit
101
(i.e., at the lower part in
FIG. 19
, and at the right side in FIG.
23
).
The cell selecting transistors
105
and
106
are n-channel conductivity type field effect transistors. The cell selecting transistor
105
includes a channel forming region, a gate insulating film
151
on the channel forming region, a gate electrode
152
on the gate insulating film
151
, and a pair of n-channel type semiconductor regions
155
functioning as a source or drain region. The gate electrode
152
is integral with a gate electrode
152
of an adjacent cell selecting transistor
105
in the same column, thereby constituting a cell selecting signal line
152
S.
The cell selecting transistor
106
includes a channel forming region, a gate insulating film
161
on the channel forming region, a gate electrode
162
on the gate insulating film
161
, and a pair of n-channel type semiconductor regions
165
functioning as a source or drain region. The gate electrode
162
is integral with a gate electrode
162
of an adjacent cell selecting transistor
106
in the same column, thereby constituting a cell selecting signal line
162
S.
On the memory cell unit
101
, a plurality of bit lines
136
are provided in the column and extend in the row which intersects the word line
124
WL. A plurality of sub-bit lines
133
under the bit lines
136
are connected to the semiconductor regions
155
via connecting hole wirings
131
. The sub-bit lines
133
are formed on a first wiring layer of an inter-level isolation layer
130
. The bit lines
136
are formed on a second wiring layer of an inter-level isolation layer
135
extending over the sub-bit lines
133
. The bit lines
136
are connected to the semiconductor region
155
at one end of the cell selecting transistor
105
via the sub-bit lines
133
and connecting hole wirings
131
.
Source lines
134
are provided on the first wiring layer of the inter-level isolation film
130
together with the sub-bit lines
133
, and are connected via the connecting hole wiring
132
to one of the semiconductor regions
165
of the cell selecting transistor
106
.
FIG. 25
to
FIG. 27
show a structure of another NAND type EEPROM, which has essentially a circuit configuration identical to that shown in
FIG. 24
, but does not include sub-bit lines
133
. Specifically, bit lines
136
are provided on a first wiring layer of an inter-level isolation film
130
, and are connected to one of semiconductor regions
155
of a cell selecting transistor
105
via a connecting hole wiring
131
. This NAND type EEPROM does not include source lines
134
but is provided with source lines
165
S integral with one of semiconductor regions
165
of an adjacent cell selecting transistor
106
in the same column.
Operations of the foregoing NAND type EEPROMs will be described with reference to FIG.
28
.
(1) First of all, existing data are erased in a memory cell array
100
of the NAND type EEPROM. Specifically, the data are simultaneously erased from the memory cells
102
in a selected memory block. For this purpose, 0V is applied to the control gate electrode
124
(the word line
124
WL) while a high voltage V
PPW
, e.g. 20V, is applied to the semiconductor substrate (well region)
110
. An FN tunnel current flows to the first gate insulating film
121
, and electrons are discharged from the floating gate electrode (charge storing section)
122
to the semiconductor substrate
110
, so that a threshold voltage of the memory cell
102
becomes negative.
(2) Thereafter, data are written (step
170
S) into the memory cells
102
connected to one word line
124
WL. Specifically, the data are separately written into the memory cells
102
connected to even-numbered bit lines
136
(e.g. BL
2
, BL
4
, . . . ) and into the memory cells
102
connected to odd-numbered bit lines
136
(e.g. BL
1
, BL
3
, . . . ). For instance, the data are simultaneously written into a plurality of even-numbered memory cells
102
connected to the selected word line
124
WL.
In order to write data “0” in the memory cells
102
, i.e. in order to make the threshold voltage thereof positive, 0V is applied to the bit lines
136
. On the other hand, in order to write data “1” in the memory cells
102
, i.e. in order not to change the threshold value thereof, a writing voltage V
CC
, e.g. 3V, is applied to the bit lines
136
. When writing data in the memory cells
102
connected to even-numbered bit lines
136
, the writing voltage V
CC
is applied to odd-numbered bit lines
136
. Further, the writing voltage V
CC
is applied to the cell selecting signal lines
152
S connected to the cell selecting transistor
105
, and a writing voltage V
PASS
, e.g. 10V, is applied to non-selected word lines
124
WL. Still further, a high writing voltage V
PPW
, e.g. 20V, is applied as pulses to the selected word line
124
WL (step
171
S).
In the memory cells
102
where data “0” is to be written, 0V is applied to the drain region (semiconductor region
125
), the channel forming regions, and the source regions (semiconductor region
125
), and a high voltage is applied between the channel forming regions and the control gate electrodes
124

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