Source-down power transistor

Details Source-down power transistor Source-down power transistor

2001-11-21

2004-02-03

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S329000, C257S330000, C257S341000, C257S342000

Reexamination Certificate

active

06686626

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a source-down power transistor having a semiconductor body with two mutually opposite surfaces in which the semiconductor body includes a semiconductor substrate of a first conduction type and at least one semiconductor layer of a second conduction type located on the substrate.
A practically realized power transistor whose source electrode is located on the “underside” of a semiconductor body, more specifically on the main surface of a semiconductor body that is opposite the main surface having a gate electrode and a drain electrode, has not been proposed heretofore. Such a MOS power transistor would nevertheless be greatly advantageous for many applications relating to cooling on a cooling lug at 0 V potential, such as, for example, in the bodywork connection in a motor vehicle. This is because, precisely in such a case, there would then be no need for electrical insulation with respect to the cooling lug. Such insulation would otherwise reduce the heat conduction.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a source-down power transistor which is distinguished by a simple construction and which can be fabricated without any difficulty.
With the foregoing and other objects in view there is provided, in accordance with the invention, a source-down power transistor, that includes a semiconductor body having a first surface and a second surface located opposite the first surface. The semiconductor body includes a semiconductor substrate and at least one semiconductor layer located on the substrate. The substrate is of a first conduction type and the at least one semiconductor layer is of a second conduction type. The first surface is located opposite the substrate. The source-down power transistor includes a first highly-doped region of the first conduction type that is located between the first surface and the semiconductor substrate. The first region extends to the substrate. The first region together with the substrate forms a source zone. The source-down power transistor includes a second highly-doped region of the first conduction type located in the at least one semiconductor layer at a non-zero distance away from the first region. The second region forms a drain zone extending from the first surface to a non-zero distance away from the substrate. The source-down power also transistor includes a plurality of narrow trenches extending between the first region and the second region. Each one of the plurality of the trenches has a longitudinal dimension extending between the first region and the second region in a longitudinal direction. The plurality of the trenches are lined with an insulating layer and are filled with a conductive material forming a gate electrode. The source-down power transistor also includes a source electrode located on the second surface of the semiconductor body.
The source-down power transistor thus has a semiconductor substrate of the first conduction type, which is preferably n
+
-doped. At least one p
−
-conducting semiconductor layer, which may have a thickness of 5 &mgr;m, is provided on the n
+
-conducting semiconductor substrate, for example, an n
+
-conducting silicon wafer. A plurality of such p
−
-conducting layers are preferably situated on the semiconductor substrate.
The p
−
-conducting layers can be fabricated epitaxially and are deposited one after the other in such a way that they each reach the specified thickness of about 5 &mgr;m. In surface regions of these epitaxially deposited layers, an n
+
-type doping is introduced by implantation at locations at which a source zone and a drain zone, respectively, are later intended to be situated. After the deposition of all of the p-conducting layers with subsequent implantation of n
+
-type dopings, a high-temperature treatment is performed, with the result that the implanted n
+
-type dopings diffuse into one another and finally form pillar-like n
+
-conducting regions. One of these regions, which reaches as far as the n
+
-conducting semiconductor substrate, constitutes a source zone, while the other region, which ends before reaching the semiconductor substrate, that is to say, for example, does not go beyond the bottommost epitaxial layer, forms a drain zone.
A multiplicity of narrow trenches are then etched in the region between the source zone and the drain zone, the longitudinal direction of which trenches runs parallel to the direction between source zone and drain zone. These trenches may have a width of about 0.1 &mgr;m to a few &mgr;m. These trenches have a depth corresponding approximately to the depth of the drain zone. The trenches are then coated, on their walls and at the bottom, with an insulating layer made of silicon dioxide, for example, and are filled with n
+
-conducting polycrystalline silicon or with another suitable conductive material. In this way, controllable current channels are produced in the at least one epitaxial layer on the side walls of the trenches.
The drain zone is then connected over the whole area to a metallization plane, and the gate electrode and the p-conducting body region from the at least one p-conducting epitaxial layer are finally contact-connected once or a number of times.
When a positive drain voltage is applied to the drain zone via the drain electrode and a positive gate voltage is applied to the gate electrode, an inversion channel is formed on the side walls of the trenches, so that a current flows there. This current can readily be controlled by changing the gate voltage. In this case, the threshold voltage of the source-down power transistor, constructed in this way, depends on the doping concentration in the at least one p-conducting epitaxial layer.
The conduction types specified can, of course, also be reversed, so that the first conduction type is the p-conduction type and the semiconductor substrate is thus p
+
-doped, for example. In this case, the epitaxial layers are n-conducting.
The drain zone can, if appropriate, also include a plurality of highly doped regions which thus form a plurality of sections. In this case, the doping of these individual sections can be set freely by the size of the mask opening during the implantation of the n
+
-type dopings. Preferably, however, these plurality of highly doped regions have a higher doping concentration with increasing distance from the trenches. An LDD construction for higher dielectric strength is possible in this way (LDD=lightly doped drain).
When a plurality of sections are used for the drain zone, at least one of the respective pillar-like regions can be provided with a “metal core” or a very highly doped polysilicon core, which, although making the fabrication method relatively complicated, nevertheless considerably reduces the on resistance of the power transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a Source-down power transistor, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.


REFERENCES:
patent: 5719425 (1998-02-01), Akram et al.
patent: 6284604 (2001-09-01), Tihanyi
patent: 0 833 386 (1998-04-01), None
patent: 8-227998 (1996-09-01), None
International Search Report for PCT/DE00/09459, issued by the European Patent Office on Jan. 17, 2001.

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