Static information storage and retrieval – Read/write circuit – Accelerating charge or discharge
Reexamination Certificate
2002-04-19
2004-02-17
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Accelerating charge or discharge
C365S191000, C365S203000, C365S202000
Reexamination Certificate
active
06693835
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to memory devices, such as DRAMs. More particularly, the present invention relates to improving the parameter measured from an active command to the READ/WRITE command (tRCD) in a DRAM.
Dynamically refreshable random access memory (DRAM) is currently highly utilized for providing rapid data storage and retrieval in computerized equipment at a reasonable cost. DRAM technology is evolving rapidly. One emergence in the DRAM field is the use of synchronous operation of the DRAM control circuitry. Integrated circuit memory devices such as synchronous dynamic random access memory devices (SDRAMs) have thousands of memory cells. Each memory cell is capable of storing data in the form of an electric charge. In order to read the data in a particular memory cell, the memory cell is selectively coupled to a sense circuit via a communication line, commonly referred to as a digit line. Typically, the sense circuit is connected to a pair of digit lines and detects a voltage differential between the digit lines caused by the stored charge. Prior to coupling a memory cell to a digit line, the pair of digit lines are equilibrated to a predetermined voltage level such as VCC/2. After the sense circuit amplifies the voltage differential on the pair of digit lines, the digit lines are coupled to data input/output (IO) communication lines for data communication with external devices. In order to accelerate the read operation, and to minimize operational power consumption, the IO lines of the SDRAM are typically equilibrated and pre-charged to an initial predetermined voltage, VCC. This allows the IO lines to quickly develop a differential voltage when coupled to the amplified digit lines.
Standard synchronous DRAMs latch and decode a row address when a row address strobe is fired via an active command and then will latch and decode the column address when column address strobe is fired via the READ/WRITE command. A critical parameter is tRCD. Parameter tRCD is measured from the ACTIVE command to when the column address is available during the READ/WRITE operation. The need always exists for minimizing the time required for a memory access, and if the time between the row address latching and the column address latching (tRCD) is reduced or optimized, without effecting system operation, the memory access time of the system can be reduced.
One problem that exists is that during the first bit of a read burst, if the digit lines are not able to reach enough of a separation before being passed onto the I/O lines, the first bit can fail, since the requisite differential voltage is not present.
FIG. 2
is a graph showing signal wave forms for various signals within a typical SDRAM during an access that demonstrate one of the problems associated with digit line separation during an initial READ/WRITE operation. As shown in
FIG. 2
, digit line pair as represented by digit line
50
(DIG) and digit line
52
(DIG*) are pre-charged to a voltage level
54
which represents approximately halfway between voltage level
56
(ground) and voltage level
58
(source voltage Vcc). Both IO lines
60
and
62
are initially pulled high, but upon IOPU signal
64
being forced off, IO line
60
is being driven high by digit line
50
and IO signal
62
is being driven low by digit line
52
. However, in the region indicated by
66
, IO signal
62
is still being pulled high via IOPU. Digit line
52
is drawn towards voltage level
58
at a time when it should be driven towards voltage level
56
. Therefore, a spike occurs in region
66
for digit line
52
, thereby decreasing charge separation of the digit pair and increasing the time before the digit lines are able to be accurately read and ultimately reach full rail separation. While IOPU is on, GCOL fires, which passes the digit voltage onto the IO lines. Since the IO lines are still actively being pulled high and the pass gate (GCOL) is on, this pulls up digit line
52
. At this time, when digit separation is a minimum (tRCD), this increase in voltage of digit line
52
greatly reduces the sense amp ability to sense and fully separate the digit lines. The smaller the differential, the slower the digits will sense (i.e. slow tRCD). As the digit lines reach greater separation, this becomes less of an issue. When the digits are dumped onto the IO lines, the digit lines have a greater separation and the effect is minimized. Thus, the IOPU and GCOL timing are extremely critical at the min tRCD case. Any overlap between IOPU and GCOL causes tRCD to slow down. Once the digits have separated fully, some overlap will have substantially no effect since the sense amps are fully on and the digit lines are at full rail.
Therefore, there exists a need to minimize tRCD while allowing the requisite unimpeded digit line separation to achieve accurate reading of all bits in a READ/WRITE operation.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for improving parameter tRCD that overcomes the aforementioned digit line separation problems.
In accordance with one aspect of the invention, a method of improving digit line pair separation during a read function in a memory device is disclosed. The method includes the steps of providing an input/output data communication line equilibrating signal for equilibrating input/output data communication lines, and pre-charging a digit line pair. The method includes, upon the firing of a column access signal during the read function, firing a signal to pull down the input/output equilibrating signal logically low in order to allow the digit line pair to separate without sharing charge from the input/output data communication lines during the read function.
In accordance with another aspect of the invention, a method of operating a memory device includes the steps of providing a clock signal, and performing equilibrate and pre-charge operations on input/output data communication lines in preparation for a memory cell access operation. The method includes initiating an active command as well as a latch-setting signal, and setting a node voltage in response to the latch-setting signal to allow equilibrate and pre-charging operation ending signal to be initiated upon a column access signal. A read function is initiated with the column access signal, and the equilibrate and pre-charge operation ending signal is also initiated based upon the column access signal.
In yet another aspect of the invention, a method of firing signals in a read command of a memory array is disclosed, and includes firing an IO equilibrating ending signal based upon a column access signal for a first bit of a data burst, and firing the IO equilibrating ending signal based upon a clock signal for subsequent bits in the data burst.
In accordance with another aspect of the invention, a memory device includes a control register, a latch for receiving a latching signal from the control register, and logical circuitry associated with the latch. The logical circuitry will generate, upon the firing of a column access signal from the control register to the logical circuitry, a signal to stop equilibrating of an input/output (IO) line to allow separation of a logical high digit line signal and a logical low digit line signal.
The method and apparatus associated with the present invention are usable for read functions in a memory device.
Various other features, objects and advantages of the present invention will be made apparent from the following detailed description and the drawings.
REFERENCES:
patent: 5544124 (1996-08-01), Zagar et al.
patent: 5751656 (1998-05-01), Schaefer
patent: 5815432 (1998-09-01), Naffziger et al.
patent: 5835440 (1998-11-01), Manning
patent: 5963493 (1999-10-01), Merritt et al.
patent: 5966724 (1999-10-01), Ryan
patent: 6023429 (2000-02-01), Mecier et al.
patent: 6055654 (2000-04-01), Martin
patent: 6154401 (2000-11-01), Casper et al.
Cowles Timothy B.
Protzman Brendan N.
Lam David
Micro)n Technology, Inc.
Whyte Hirschboeck Dudek SC
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