Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-28
2004-02-03
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C326S031000
Reexamination Certificate
active
06687883
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor devices, and more specifically, to a system and method for reducing leakage current in a semiconductor device by providing reduction control circuitry in accordance with a probability determination.
2. Discussion of the Prior Art
Two main approaches have been proposed for reducing leakage currents: threshold voltage control, and logic state control.
Since leakage current in integrated circuits is inversely proportional to the threshold voltage of FETs, raising the threshold voltage may reduce leakage current. However, raising the threshold voltage also decreases the performance of the device. Therefore, passive threshold voltage control methods typically comprise selecting a portion of the non-timing critical logic paths, and using higher threshold devices for that portion of the circuit. Active threshold control methods also exist in which the threshold voltage is dynamically adjusted by active body or well biasing when the chip is in a “stand-by” or “sleep” mode where full-performance is not required of the circuit and minimum leakage is desired.
Logic state control for leakage is based on the concept that a circuit's leakage is highly dependent on the state of its inputs. For example, a CMOS two-way NAND gate may have an order of magnitude less leakage current when both inputs are at a low voltage than when they are both at a high voltage. Leakage control in these methods consists of finding a set of logic values which, when applied to a logic network at its inputs, produces the lowest leakage state possible given the logic network. The set of logic values that causes this “low leakage state” may be called the “low leakage vector”. The low leakage vector is applied to the network when the chip enters the “stand-by” or “sleep” modes of operation, by means of modified storage elements which force the low leakage vector onto the network.
One of the main challenges with this approach is finding the low leakage vector on large logic circuits. Since the number of possible logic states is directly proportional to the number of inputs to the circuit, it is impractical, if not impossible, to exhaustively check all possible states. Thus, heuristic algorithms have been developed to explore the state space and find “low leakage vectors”. These algorithms are limited by the fact that they can only control the inputs to the circuit and thus will likely not find the “lowest leakage vector” possible.
Another limitation of the logic state control approach is that the distinction between “sleep” and “active” states is not always clear. Different parts of the design will be inactive (i.e., in a sort of “sleep” mode) for different amounts of time. In new technologies where the relative importance of leakage power relative to active switching power is increasing, reducing leakage of these inactive portions of the network becomes important even for relatively short periods of time.
In previous systems, leakage reduction techniques have focused on statically determining a low leakage vector that can be applied to the design upon entering a “standby” state, by means of forcing the storage elements to the low leakage vector.
There are techniques in the art that utilizes probabilistic information about the network state for optimizing digital circuit design. One reference in particular by S. Sirichotiyakul, T. Edwards, et al. entitled “Stand-by Power Minimization through Simultaneous Threshold Voltage Selection and Circuit Sizing”. ACM 1999, Ch. 26.2, pp. 436-441. Specifically, this reference teaches that a probabilistic analysis may be used to size transistors and change voltage thresholds in order to reduce or minimize leakage. However, this prior art reference is not concerned with the circuit sleep state nor is it concerned with the setting of the logic state of signals in order to minimize leakage.
It would therefore be highly desirable to provide improved methods and mechanisms for finding a low leakage vector by using probabilistic approaches to find the expected leakage of integrated circuit devices at any point in time, based on logic state statistics.
It would therefore be highly desirable to provide an improved method and mechanism that allows manipulation of logic that results in changes to the probabilities so that the circuit may be in an optimized state, either globally or locally, when the semiconductor circuit is in an idle condition.
Furthermore, it would be highly desirable to provide improved methods and mechanisms for finding a low leakage vector by using probabilistic approaches that permit logic optimization for reducing leakage current even while the circuit is “active”, thus accommodating the indistinct line between “sleep” and “active” mode operation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a logic system design methodology that forces the states of logic gates based on a probabilistic analysis in order to reduce the leakage.
It is a further object of the present invention to provide a method and mechanism for finding leakage probabilities during synthesis to modify the network such that it results in a lower leakage design during any of the many active/semi-active/standby states.
It is another object of the present invention to provide a logic system design methodology implementing a probabilistic analysis for reducing the leakage during any of the many active/semi-active/standby states without making device accommodations, or adding special switches, to result in a lower overhead.
It is yet another object of the present invention to provide a method and mechanism for forcing the logic states exploiting the intrinsic nature of the gates during synthesis to modify the network such that it results in a lower leakage design.
The present invention overcomes the difficulty of finding the exact low leakage vector by using probabilistic approaches to find the expected leakage at any point in time, based on logic state statistics. This enables logic optimization to reduce leakage current even while the circuit is “active”, thus accommodating the indistinct line between “sleep” and “active” mode operation. The probabilistic information may be computed and stored by several techniques not unlike those techniques used to determine switching information for analysis of switching power. Information may be gathered on individual nets as a result of a simulation trace. Alternatively, the probabilities of various input states (sets of primary input and latch output logical values) may be tracked in order to keep track of correlations between signals. Such input state information may be stored compactly using binary decision diagrams (BDDs) or other well-known means. Given for each signal the probability of that signal being at a particular value (either independent of all other signal values or correlated through state information) and information for each block in the logic network about the leakage of that block for each possible combination of input values, the estimated leakage power may be computed by summing over all blocks: the sum over all combinations of block input values of the leakage under that combination of input values multiplied by the probability of occurrence of that combination of input values. As changes are made to the logic network which affect these signal probabilities, the probabilities may be updated and the resulting change in leakage power may be estimated. The signal probability updates may be achieved by re-simulating part or all of the logic network, by recomputing probabilities on nets in the fanout cone of logic changes based on updated probabilities at the inputs of the gates driving the nets, by some combination of these, or by other means.
Along with signal probabilities, and in a similar manner, there is computed, for each state, the probability that any given signal net will switch when the network is in that state. Again, this may be done by treating the various nets in the network independently in which
Cohn John M.
Dean Alvar A.
Hathaway David J.
Ventrone Sebastian T.
International Business Machines - Corporation
Kotulak, Esq. Richard M.
Scully Scott Murphy & Presser
Thompson A. M.
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