Container capacitor

Details Container capacitor Container capacitor

1998-03-02

2004-06-29

Tran, Thien F (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S309000

Reexamination Certificate

active

06756627

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to methods of forming a conductive structure over a charge conducting region. More particularly, the present invention relates to methods of forming a vertically oriented structure composed of conductive material projecting from a charge conducting region. The method of the present invention is particularly useful for forming a capacitor storage node between two gate stacks situated on a semiconductor substrate.
2. The Relevant Technology
Integrated circuits provide the logic and memory of computers and other intelligent electronic products. These tiny chips have advanced in capability to a level that has made the computers and other intelligent electronic devices in which the integrated circuits operate highly functional. Integrated circuits are also being manufactured economically, allowing the highly functional computers and other intelligent electronic products to be provided to consumers at an affordable cost.
Integrated circuits are currently manufactured by an elaborate process in which semiconductor devices, insulating films, and patterned conducting films are sequentially constructed in a predetermined arrangement on a semiconductor substrate. In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including but not limited to the semiconductor substrates described above. The conventional semiconductor devices which are formed on the semiconductor wafer include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor substrate.
The computer and electronics industry is constantly under market demand to increase the speed at which integrated circuits operate, to increase the capabilities of integrated circuits, and to reduce the cost of integrated circuits. One manner of accomplishing this task is to increase the density with which the semiconductor devices can be formed on a given surface area of a single semiconductor wafer. In so doing, the semiconductor devices must be decreased in dimension in a process known as miniaturization. In order to meet market demands and further the miniaturization of integrated circuits, the processes by which the semiconductor devices are formed are in need of improvement. The challenge in miniaturizing integrated circuits is to do so without greatly increasing the cost of the processes by which integrated circuits are manufactured. Accordingly, the new processes must also be relatively simple and cost effective.
One structure which is frequently formed in integrated circuit manufacturing and for which improved methods of formation are needed is the capacitor. The capacitor is formed with a storage node, a cell plate, and an intervening dielectric layer. The storage node and the cell plate are typically patterned out of polysilicon by conventional photolithography and dry etching. The dielectric layer is formed in an intervening process between the formation of the storage node and the cell plate, typically by growth of silicon dioxide through exposure of the polysilicon of the storage node to oxygen at an elevated temperature.
An important consideration in forming capacitors in integrated circuits is surface area. A large surface area of the storage node and cell plate is necessary in order to provide high capacitance and therefore optimal performance of the capacitor. Balanced against this need is the competing requirement that the capacitor also occupy a minimum of space on the semiconductor substrate on which the capacitor is formed. One manner in which the semiconductor industry has approached minimal space capacitor formation is to form the capacitor at a significant distance above the semiconductor substrate. When so doing, one of the storage node and the cell plate are typically wrapped around the other, forming what is known as a stacked capacitor.
The use of container capacitors has effectively increased capacitor surface area, but the formation of container capacitors presents new problems. One such problem involves making electrical contact between the container capacitor and an underlying source/drain region through a relatively narrow area between two gate stacks. One example of the occurrence of such a problem is in the formation of a metal oxide silicon dynamic random access memory (MOS DRAM) cell, where a container capacitor is formed above two word line gate stacks.
Shown in
FIG. 1
is a typical arrangement of the basic structure used in the formation of a MOS DRAM memory cell. Shown therein is semiconductor structure
10
formed with a silicon substrate
12
on which are located a plurality of source/drain regions
12
a
. A pair of gate stacks, generally seen at reference numeral
14
, serve as word lines and provide control signals to the memory cell. Gate stacks
14
are situated on silicon substrate
12
, one gate stack
14
at either side of the center source/drain region
12
a
. Each gate stack
14
is provided at the top and sides thereof with a protective silicon nitride spacer
14
a
. Miniaturization demands require that gate stacks
14
be closely spaced. Thus a relatively narrow open space
16
is defined between gate stacks
14
and over the center source/drain region
12
a.
Typically in the formation of a container capacitor, a storage node is formed above source/drain region
12
a
projecting upwards therefrom for a distance above gate stacks
14
. To form the storage node, a layer of insulating material such as a borophosphosilicate glass (BPSG) layer is formed over gate stacks
14
and source/drain region
12
a
therebetween. Open space
16
, seen in
FIG. 1
, is then etched into the BPSG layer in which to form the container capacitor. Open space
16
extends from the top most surface of the BPSG layer down to source/drain region
12
a
in between gate stacks
14
. Once formed, the storage node will be situated upon source/drain region
12
a
in between gate stacks
14
.
Problems arise in removing BPSG material to form open space
16
which is typically narrower than about 0.2 microns, a distance not readily achievable with conventional photolithography resolution. Therefore, in order to form open space
16
, the BPSG layer must be patterned such that the subsequent etch of the BPSG layer creates an opening above open space
16
that is wider than open space
16
. If the etch of the BPSG layer is selective to silicon nitride cap
14
a
, the etch form open space
16
such that it is self-aligned between gate stacks
14
. Self-alignment ensures that, if the etched opening above open space
16
is slightly misplaced in initial alignment between gate stacks
14
and the source/drain region
12
a
therebetween, open space
16
will still be situated between gate stack
14
so as to expose source/drain region
12
a
therebetween.
Conventional self-alignment processes have several drawbacks which are advantageous to avoid. For instance, a dry etching process such as reactive ion etching (RIE) or milling RIE (MRIE) is typically used to form the opening to open space
16
, and must also clear BPSG material from open space
16
. In so doing, it is difficult to terminate the dry etching without etching into the silicon of source/drain region
12
a
between gate stacks
14
. It is also difficult to maintain a uniformity of the dry etching process across the entirety of semiconductor structure
10
when etching into multiple open spaces
16
situated across semiconductor structure
10
, such that all open spaces
16
are fully cleared of BPSG material without etching into respective source/drain regions
1

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