Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-11-19
2004-11-23
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C250S306000, C250S491100, C324S1540PB, C438S015000, 36
Reexamination Certificate
active
06822260
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the manufacturing of semiconductor devices, and more particularly, to forming strained-silicon devices having improved characteristics.
BACKGROUND OF THE INVENTION
Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices, and the most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is a metal-oxide-semiconductor(MOS) transistor. The MOS transistor is one of the basic building blocks of most modern electronic circuits. Importantly, these electronic circuits realize improved performance and lower costs, as the performance of the MOS transistor is increased and as manufacturing costs are reduced.
A typical MOS device includes a bulk semiconductor substrate on which a gate electrode is disposed. The gate electrode, which acts as a conductor, receives an input signal to control operation of the device. Source and drain regions are typically formed in regions of the substrate adjacent the gate electrodes by doping the regions with a dopant of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region. The typical MOS device is symmetrical, in that the source and drain are interchangeable. Whether a region acts as a source or drain typically depends on the respective applied voltages and the type of device being made. The collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
During the manufacturing process, a semiconductor device undergoes many types of metrology tests to ensure the quality of the semiconductor device. For example, processes, such as lithography, are controlled, in part, by taking dimensional measurements of certain features of the semiconductor device formed by the lithography process. One type of measurement technique used to measure the dimensions of a structure in a semiconductor device is scatterometry. Scatterometry is a non-destructive optical technique that records and analyzes changes in the intensity of light reflected from a periodic scattering surface. By measuring and analyzing the light diffracted from a patterned periodic sample, the dimensions of the sample structure can be measured. Other types of measurement techniques used to measure the dimension of a structure are electrical tests, known as I-force and V-measure. These tests use known parameters, such as length of a line, and calculated parameters, such as sheet resistance, to calculate line width based on voltage drop across electrodes connected to the line. These different types of metrology tests, however, use different structures on the semiconductor device. As such, cross-correlating the results of these metrology tests has not been possible. Furthermore, the width of the lines in two different test structures can vary as a result of process used to form the lines. As the size of structures are becoming increasingly smaller, the variation in line width introduced by the manufacturing process becomes increasingly significant to the accuracy of the testing. Accordingly, a need exists for an improved semiconductor device and method of forming the same that allows for cross-correlation of results from different types of metrology tests and eliminates line width disparity between two different test structures.
SUMMARY OF THE INVENTION
This and other needs are met by embodiments of the present invention which provide a method of manufacturing a semiconductor device that allows for a direct comparison of a line width calculated by optical scatterometry metrology and a line width calculated by an electrical line width measurement test. The method includes depositing a layer over a substrate and etching the layer to form a grating structure, a cross bridge test structure and a line width measurement structure. The grating structure includes a plurality of parallel lines and one of the multiple parallel lines is connected to the line width measurement structure and the cross bridge test structure. A scatterometry test is performed on the grating structure to obtain a line width and this width is compared to a line width calculated using the line width measurement structure.
In another embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a grating structure with a plurality of parallel lines. One of the parallel lines is connected to a line width measurement structure. The line is also connected to a sheet resistance test structure. The line width measurement structure is formed from first and second pairs of electrodes, and the sheet resistance test structure is a cross bridge test structure formed from the second pair of electrodes and a third pair of electrodes.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 4516071 (1985-05-01), Buehler
patent: 5920067 (1999-07-01), Cresswell et al.
patent: 6057171 (2000-05-01), Chou et al.
Nariman Hormuzdiar E.
Wristers Derick J.
Flynn Nathan J.
Wilson Scott R
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