Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-12-30
2004-11-30
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06826731
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of generating an interface between circuit blocks in designing a large-scale semiconductor integrated circuit device by using circuit blocks, which are existing resources for designing a circuit such as IPs (Intellectual Properties).
To reduce the number of designing steps, the development of such a large-scale integrated circuit device as termed, e.g., “system LSI” using circuit blocks termed IPs (or IP cores), which are existing resources for designing a circuit, has been started recently. The circuit blocks have predetermined input/output interfaces (I/F) which are normally different from one circuit block to another. In incorporating such circuit blocks having different interfaces into one system, therefore, it is an important design issue how to adjust the I/F of the individual circuits blocks and thereby promote smooth signal transmission between the individual circuit blocks. For example, it is necessary to modify logics and timings for I/F adjustment in incorporating the circuit blocks into one system.
To meet the necessity, a designing operation has been performed conventionally by a designer who recognizes input/output logics and timings of the circuit blocks, fully understands the difference in I/F structure between the individual circuits blocks, and newly designs an interface circuit or the like required to incorporate the circuit blocks such that the difference in I/F structure between the individual circuit blocks is absorbed and the connecting states between the individual circuit blocks are retained.
As a system LSI to be designed has been scaled up increasingly in recent years, however, the number of circuit blocks to be incorporated into the system LSI has also been increased exponentially. If an adjustment between the individual circuits is performed manually, an enormous amount of designing operation should be performed. In other words, it has been becoming difficult to efficiently design a large-scale integrated circuit device such as a system LSI by a conventional designing method which depends only on the skills of the designer.
On the other hand, there has been known such technology as follows which focuses attention on circuit behaviors such as the attributes and timings of signals and generates a new circuit from the circuit behaviors.
For example, Japanese Unexamined Patent Publication No. HEI 6-32972 discloses technology for generating a new hardware description language from a timing chart and the attributes of signals.
Japanese Unexamined Patent Publication No. HEI 7-253998 discloses technology for synthesizing, by using a truth table, behavioral descriptions of two or more logic circuits newly generated and thereby producing a new, complete circuit behavioral description.
Japanese Unexamined Patent Publication No. HEI 9-91355 discloses technology for generating circuit data, expected value data, timing data, or the like based on operational data, performing simulation, and automatically generating a new logic circuit.
In view of the foregoing, there can be considered the generation of a circuit for absorbing a difference in I/F structure between the circuit blocks by using the conventional methods of automatically generating circuits mentioned above.
Although the technology disclosed in the foregoing conventional publications allows generation of a new circuit block independent of the circuit blocks, the matter of how to smoothly retain the connecting states between the individual blocks remains to be solved. With the conventional technologies, it is difficult to generate an interface circuit considering a difference in I/F structure between the individual circuit blocks in the design of an integrated circuit device using circuit blocks which are existing resources.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to improve, in the design of an integrated circuit device using circuit blocks which are existing resources, an efficiency with which a large-scale integrated circuit device is designed with the provision of means which allows easy correction or modification of an existing circuit considering an interface structure and easy generation and insertion of a new interface circuit between circuit blocks without recognizing the input/output logics, timings, and the like of the circuit blocks.
A first method of designing a semiconductor integrated circuit device of the present invention is a method of designing a semiconductor integrated circuit device by using at least two circuit blocks stored in a database, the method comprising the steps of: (a) generating an interface circuit for implementing, in response to an operation of modifying a timing chart for providing a coincidence between a timing relationship between input signals or output signals of a first circuit block and a timing relationship between input signals or output signals of a second circuit block, a content of the modification in the timing chart; and (b) automatically inserting the interface circuit generated in the step (a) between the first and second circuits.
If a semiconductor integrated circuit device is to be constructed by using a plurality of circuit blocks such as IPs having different timing characteristics, the method allows automatic insertion of an interface circuit for providing smooth transmission of data between the circuit blocks. Accordingly, the number of designing steps is reduced greatly and a designing method suitable for the construction of a large-scale semiconductor integrated circuit device, such as a system LSI, is provided.
A second method of designing a semiconductor integrated circuit device of the present invention is a method of designing a semiconductor integrated circuit device by using at least two circuit blocks stored in a database, the method comprising the steps of: (a) generating an interface circuit for implementing, in response to an operation of modifying a timing chart for providing a coincidence between a timing relationship between input signals or output signals of a first circuit block and a timing relationship between input signals or output signals of a second circuit block, a content of the modification in the timing chart; and (b) adding the interface circuit generated in the step (a) to the first or second circuit block.
If a semiconductor integrated circuit device is to be constructed by using a plurality of circuit blocks such as IPs having different timing characteristics, the method allows generation of a new circuit block by adding, to the circuit block, an interface circuit for providing smooth transmission of data between the circuit blocks. Consequently, the number of designing steps is reduced greatly, while the number of components required to design the semiconductor integrated circuit device is reduced, so that a designing method suitable for the construction of a large-scale semiconductor integrated circuit device, such as a system LSI, is provided.
The second method further comprises the step of: storing, in the database, the first or second circuit block having the interface circuit added thereto as a new circuit block. This allows the corrected circuit block to be re-used to design another semiconductor integrated circuit device.
The step (b) includes determining either of the first and second circuits as the circuit to which the interface circuit is to be added based on a preset parameter. This allows the designing of a semiconductor integrated circuit device in which the parameter to which the user attaches importance is optimized.
The step (b) includes using a layout area as a parameter. This allows design even conscious of layout.
The step (b) includes using, as a parameter, a variation in a number of pins in the first or second circuit block. This allows design conscious of the number of pins.
If at least one other circuit block in addition to the first and second circuit blocks is disposed in the integrated circuit device, the step (b) includes using, as a parameter, a number of circuit blocks to each of
Arita Miki
Hamada Mana
Ohashi Masahiro
Sugisawa Yuji
Tojima Masayoshi
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Siek Vuthe
LandOfFree
Method of designing semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of designing semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of designing semiconductor integrated circuit device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3298017