Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2002-08-06
2004-08-31
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S459000, C257S786000, C257S673000, C438S123000, C361S813000
Reexamination Certificate
active
06784533
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device which is structured to connect pads with bumps for outside connection by wiring sections in a semiconductor element and more particularly to the semiconductor device which may reduce the operating noise even if its clock frequency is several hundred MHz or more.
In recent days, semiconductor devices have been more and more requested to enhance its density, integration and speed and lower its cost. In order to meet with the request, for example, as disclosed in JP-A-8-250498, a semiconductor device has been designed so that wiring sections and bumps are formed on a pad forming surface of a semiconductor element and those wiring sections and bumps are conductive with the pads. As shown in
FIG. 17
, in such a technology, a pad forming surface of a semiconductor element is formed to have a plurality of pads, and a plurality of wiring sections are formed on the pad forming surface so that those wiring sections may make a continuity with one of those pads. The bumps are formed at predetermined positions in the wiring sections so that those bumps may be formed at any interval without being limited by the positions and the intervals of the pads merely by prescribing those predetermined positions. The outer dimension of the semiconductor device is, therefore, the substantially same as the dimension of the chip on which the semiconductor element is mounted, so that the semiconductor device may be manufactured in higher density and integration and lower cost.
In order to reduce the power noise of an LSI chip and make the operation faster, for example, as disclosed in JP-A-6-163822, a planar power wiring pattern is formed on the substantially overall surface of the chip except signal electrode pads. This technology as shown in
FIG. 18
provides a capability of directly supplying an electric power from the planar power surface to a circuit element located under the planar power surface, which leads to reducing the inductance and the power noise of the LSI chip, thereby making the operation of the semiconductor device faster.
As described above, the conventional semiconductor devices may be composed in higher density and integration and lower cost by forming the pads, the bumps and the wiring sections on the pad forming surface of the semiconductor element. However, those semiconductor devices still have a problem in speed.
For example, if a semiconductor device provided with a supply voltage of 3.3 V is operated at a clock frequency of 200 MHz, roughly speaking, it is necessary to switch a signal voltage from a high state (supply voltage) to a low state (ground voltage) merely for a time of 500 ps corresponding to 10% of a clock period 5 ns. Assuming that the load capacitance at this time is about 10 pF, the charges to be charged in this capacitance may be calculated as 10 pF×3.3 V=33 pC. The current flowing in the switching is represented by differentiating the charges in time, that is, 33 pC/500 ps=0.066 A. It is known that this kind of transient current flow in switching a signal may give rise to a noise voltage by the inductance of the wiring system and thereby serves to malfunction the semiconductor device, for example, as described in E. E. Davidson et al., IBM J. Res. Dev. May 1982, vol. 26. This noise voltage may be represented by a time-base change rate of the inductance and the transient current. For example, assuming that the inductance of one lead of the semiconductor device is 10 nH, a noise voltage of about 1.3 V per lead is generated. This noise voltage may be derived by 10 nH×0.066 A/500 ps. If this kind of noise appears in the power supply, the ground or the signal line, the actual high or low state is erroneously read. This may lead to malfunction. As mentioned above, this noise is roughly in proportion to the operating speed, that is, the operating frequency. Hence, in order to reduce the operating frequency, the operation speed cannot be made faster. Hence, for making the operation speed faster, it is necessary to reduce another parameter for determining the noise, that is, the inductance of the wiring system provided in the semiconductor device.
The foregoing semiconductor device disclosed in JP-A-8-250498 may provide a smaller semiconductor device than the conventional surface mounting type semiconductor device by forming the pads, the bumps and the wiring sections on the pad forming surface. It means that the inductance of the wiring system is reduced as compared with the conventional surface mounting type semiconductor device. However, considering that a conductor having a length of several millimeters contains roughly several nH inductance, the foregoing semiconductor does not provide so low an inductance as meeting the request by the recent various systems that need to operate at a quite fast speed.
Further, the semiconductor device disclosed in JP-A-6-163822 considers reduction of the inductance on the power wiring side. However, it does not consider reduction of the inductance on the ground wiring side. Hence, the semiconductor device has no means of reducing the noise caused on the ground wiring side. Further, the pads are scattered on the chip surface and when this chip is mounted on the mounting substrate by bumps or the like, those bumps are scattered as well. It means that the planar conductive layer cannot be easily formed.
SUMMARY OF THE INVENTION
In consideration of the foregoing problem, it is an object of the present invention to provide a semiconductor device which contains a lower inductance of the wiring system for the purpose of meeting with the requests of high density and integration, low cost and the like without making the manufacturing process complicated as well as making the semiconductor device operate at a faster clock frequency than several hundreds MHz as keeping its noise low. Further, the present invention provides a capability of reducing the noises generated on the power wiring side as well as the ground wiring side. Moreover, the invention also provides the solving method for a general structure having difficulty in reducing the inductance on the wiring system because of the pads and bumps located on the chip surface.
In carrying out the foregoing object, the semiconductor device according to the invention of the present application is characterized by including the following structures:
(1) In a semiconductor device including a semiconductor element having power pads for supplying a power potential, ground pads for supplying a ground potential, signal pads for inputting and outputting a signal, all of which are formed on one main surface thereof; power bumps for outside connection being connected with the power pads by power wiring sections; ground bumps for outside connection being connected with the ground pads by the ground wiring sections; and signal pads for outside connection being connected with the signal pads by signal wiring sections, the power wiring section or the ground wiring section is located adjacently on both sides of the signal wiring sections.
(2) In a semiconductor device having a plurality of pads, a plurality of bumps, and a plurality of wiring sections for connecting the pads with the bumps, all of which are formed on one main surface of the semiconductor element, the plurality of pads include power pads, ground pads and signal pads, the plurality of wiring sections include power bumps, ground bumps and signal bumps, the plurality of wiring sections include power wiring sections, ground wiring sections and signal wiring sections, and the power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.
(3) In (1) or (2), the ground wiring sections and the signal wiring sections are both located on one main surface of the semiconductor element through several n-type layer.
(4) In (1) or (2), the power wiring sections and the ground wiring sections and the signal wiring sections are located on one main surface of the semiconductor
Miura Hideo
Miyamoto Tosiho
Nishimura Asao
Shimizu Hiroya
Tanaka Hideki
Antonelli Terry Stout & Kraus LLP
Clark Jasmine
Renesas Technology Corp.
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