Multi-level memory cell with lateral floating spacers

Details Multi-level memory cell with lateral floating spacers Multi-level memory cell with lateral floating spacers

2002-12-20

2004-12-14

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S320000, C257S296000, C257S314000, C257S316000

Reexamination Certificate

active

06831325

ABSTRACT:

TECHNICAL FIELD
The invention relates to semiconductor integrated memory cells and, in particular, to multibit charge storage transistors.
BACKGROUND ART
In the past, nonvolatile memory transistors stored only one binary bit. In EEPROM (electrically eraseable programmable read only memory) transistors such charge storage occurs on a floating gate and so, such transistors are referred to as floating gate memory cell transistors. In order to store two binary bits in an EEPROM transistor, some modification of the transistor design is needed. Multibit charge storage transistors are known, including nonvolatile multibit transistors.
In U.S. Pat. No. 6,323,088, Gonzalez et al. teach the use of two floating gates, placed side-by-side, beneath a control gate to form a multi-level memory cell. The control gate is connected to a word line over both of the floating gates while the active subsurface source and drain regions are connected to respective digit lines. By appropriately controlling the voltage and timing applied to the word line and the digit lines, separate charges can be stored and read from each of the two floating gates of the single transistor. Use of the two floating gates allows storage of two independent bits of information by separately controlling charge stored in each of the two floating gates.
In U.S. Pat. No. 6,178,113, Gonzalez et al. teach another type of multi-level memory cell. Once again a pair of floating gates are provided beneath a control gate, with electrode connections as in the previously mentioned patent. However, here one or each of the floating gates is associated with a side insulator and an associated doped region next to the insulator, forming a capacitor across the side insulator with a floating gate. So now the structure has the properties of side-by-side capacitive structures fabricated as a single EEPROM transistor but with multi-level storage.
While the above structures are significant contributions to the state of the art, even more compact structures are needed for embedded memory applications. In embedded memory, a circuit board might have a principal function, such as a processor function or a communications function. Frequently such boards contain microprograms to control operation or to store data. It is desirable to provide a single chip with high-density memory, rather than to rely on a plurality of separate memory chips. While use of multi-level memory chips would provide a solution, such chips are often larger than conventional transistors and so part of the advantage of such a solution is lost. An object of the invention was to devise a nonvolatile multi-level memory transistor, particularly an EEPROM, that is comparable in size to single bit nonvolatile memory chips.
SUMMARY OF THE INVENTION
The above object has been met with a nonvolatile memory transistor that uses a pair of polysilicon floating spacer structures for storage of two data bits. The two spacers are on opposite sides of a single central conductive gate, but separated from the conductive gate by tunnel oxide having a thickness in the range of 10-50 angstroms. Tunnel oxide also separates the floating spacer structures from subsurface source and drain electrode regions. In this arrangement, the spacers themselves behave as principal conductive charge storage floating members on either side of the single central gate that is wired to be the control gate. In this manner the two binary bit lateral charge storage members of the present invention use approximately the same space as a conventional EEPROM cell using nitride or oxide spacers, while not increasing vertical dimensions. Charge is stored and isolated within the floating spacers by tunneling action with respect to both the substrate and the central gate. The control gate is wired as a word line, while the subsurface source and drain regions are the digit lines which are each connected to auxiliary transistors controlling phases for addressing each side of the memory cell independently.


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