Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2002-02-14
2004-10-05
McLean-Mayo, Kimberly (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S103000, C711S154000, C365S189040, C365S189011, C365S230010
Reexamination Certificate
active
06801979
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to nonvolatile memory arrays, and, in particular, to control circuits for increasing the speed of operations performed on the nonvolatile memory arrays.
BACKGROUND OF THE INVENTION
In the conventional method of accessing memory arrays (including flash memory arrays), whether it be a read or write operation, each operation is performed sequentially, meaning that an operation has to be completed before the start of the next read or write operation. In performing an operation to access a memory array, the given data address is first decoded and the decoded address is provided to the memory array for fetching the data or storing the data. Because each of the decoding and accessing steps are done in a sequential manner, these architectures of the prior art memory arrays do not lend themselves to faster throughputs necessary for modern day high-speed memory access and throughput requirements.
Therefore, it would be desirable to have a method and memory architecture conducive to high-speed memory throughput not limited to the sequential speed of each memory access.
SUMMARY OF THE INVENTION
It is the object of the present invention to provide a method and architecture for high speed accessing of a memory array with respect to write-to-memory and read-from-memory operations.
It is another object of the present invention to provide a method and architecture for high speed accessing of a memory array that allows for continuous read or write operations from and to the memory array.
It is yet another object of the present invention to provide a method and architecture for high speed accessing of a memory array, which allows for continuously decoding of data addresses for reading or writing from and to the memory array.
It is still another object of the present invention to provide a method and architecture, which allows for the decoding of a data address while the data addressed by the previous data address is being accessed.
Briefly, the presently preferred embodiment of the present invention provides a method and architecture for fast memory access (read or write) of the data to and from a memory array. Architecture wise, the memory array control circuit provides for at least two address latches and two page registers. The first address latch contains a first data address and the second address latch contains a second data address. The first data address is decoded first and sent to the memory array to access (read or write) the corresponding data from the memory array. When the data of the first data address is being accessed, the decoding process will begin for a second data address. When the data of the first data address has been accessed, the second data address is ready for the memory array. Thus, there can be continuous fetching from or writing to the memory array. In the preferred embodiment, there are two page registers. In a read operation, the data read from the first data address is transferred to a first page register. When the data of the second data address is being accessed, the data in the first page register is transferred to a second page register. When the operation to read the data from the second data address is completed, the data can be placed in the first register. The data in the second page register can be rapidly transferred to a latch and on to a bus. In this manner, there is always space made available for the data read. Similarly, in a write operation, data is transferred from the data bus to the second page register and then to the first page register. The data in the first register is written into the memory array.
An advantage of the present invention is that it provides a method and architecture for high speed accessing of a memory array with respect to write-to-memory and read-from-memory operations.
Another advantage of the present invention is that it provides a method and architecture for high speed accessing of a memory array that allows for continuous read or write operations from and to the memory array.
Yet another advantage of the present invention is that it provides a method and architecture for high speed accessing of a memory array, which allows continuously decoding of data addresses for reading or writing from and to the memory array.
Still yet another advantage of the present invention is that it provides a method and architecture, which allows for the decoding of a data address while the data addressed by the previous data address is being accessed.
These and other features and advantages of the present invention will become well understood upon examining the figures and reading the following detailed description of the invention.
REFERENCES:
patent: 3633175 (1972-01-01), Harper
patent: 4006457 (1977-02-01), Hepworth et al.
patent: 4013902 (1977-03-01), Payne
patent: 4210959 (1980-07-01), Wozniak
patent: 4250570 (1981-02-01), Tsang et al.
patent: 4279024 (1981-07-01), Schrenk
patent: 4281398 (1981-07-01), McKenny et al.
patent: 4295205 (1981-10-01), Kunstadt
patent: 4309627 (1982-01-01), Tabata
patent: 4354253 (1982-10-01), Naden
patent: 4355376 (1982-10-01), Gould
patent: 4380066 (1983-04-01), Spencer et al.
patent: 4392208 (1983-07-01), Burrows et al.
patent: 4405952 (1983-09-01), Slakmon
patent: 4422161 (1983-12-01), Kressel et al.
patent: 4450559 (1984-05-01), Bond et al.
patent: 4456971 (1984-06-01), Fukuda et al.
patent: 4462086 (1984-07-01), Kurakake
patent: 4463450 (1984-07-01), Haeusele
patent: 4479214 (1984-10-01), Ryan
patent: 4493075 (1985-01-01), Anderson et al.
patent: 4498146 (1985-02-01), Martinez
patent: 4514830 (1985-04-01), Hagiwara et al.
patent: 4525839 (1985-07-01), Nozawa et al.
patent: 4527251 (1985-07-01), Nibby, Jr. et al.
patent: 4586163 (1986-04-01), Koike
patent: 4601031 (1986-07-01), Walker et al.
patent: 4612640 (1986-09-01), Mehrotra et al.
patent: 4616311 (1986-10-01), Sato
patent: 4617624 (1986-10-01), Goodman
patent: 4617651 (1986-10-01), Ip et al.
patent: 4642759 (1987-02-01), Foster
patent: 4654847 (1987-03-01), Dutton
patent: 4672240 (1987-06-01), Smith et al.
patent: 4688219 (1987-08-01), Takemae
patent: 4710871 (1987-12-01), Belknap et al.
patent: 4718041 (1988-01-01), Baglee et al.
patent: 4727475 (1988-02-01), Kiremidjian
patent: 4733394 (1988-03-01), Giebel
patent: 4740882 (1988-04-01), Miller
patent: 4746998 (1988-05-01), Robinson et al.
patent: 4748320 (1988-05-01), Yorimoto et al.
patent: 4757474 (1988-07-01), Fukushi et al.
patent: 4774700 (1988-09-01), Satoh et al.
patent: 4785425 (1988-11-01), Lavelle
patent: 4794568 (1988-12-01), Lim et al.
patent: 4796233 (1989-01-01), Awaya et al.
patent: 4800520 (1989-01-01), Iijima
patent: 4814903 (1989-03-01), Kulakowski et al.
patent: 4849927 (1989-07-01), Vos
patent: 4887234 (1989-12-01), Iijima
patent: 4896262 (1990-01-01), Wayama et al.
patent: 4914529 (1990-04-01), Bonke
patent: 4920518 (1990-04-01), Nakamura et al.
patent: 4924331 (1990-05-01), Robinson et al.
patent: 4942556 (1990-07-01), Sasaki et al.
patent: 4943962 (1990-07-01), Imamiya et al.
patent: 4945535 (1990-07-01), Hosotani et al.
patent: 4949240 (1990-08-01), Iijima
patent: 4949309 (1990-08-01), Rao
patent: 4953122 (1990-08-01), Williams
patent: 4958323 (1990-09-01), Sugawara et al.
patent: 5003591 (1991-03-01), Kauffman et al.
patent: 5034926 (1991-07-01), Taura et al.
patent: 5043940 (1991-08-01), Harari
patent: 5053990 (1991-10-01), Kreifels et al.
patent: 5058074 (1991-10-01), Sakamoto
patent: 5070474 (1991-12-01), Tuma et al.
patent: 5095344 (1992-03-01), Harari
patent: 5134589 (1992-07-01), Hamano
patent: 5138580 (1992-08-01), Farrugia
patent: 5155705 (1992-10-01), Goto et al.
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5168465 (1992-12-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5198380 (1993-03-01), Harari
patent: 5200959 (1993-04-01), Gross et al.
patent: 5226168 (1993-07-01), Kobayashi et al.
patent: 5268318 (1993-12-01), Harari
patent: 5268870 (1993-12-01), Harari
patent: 5268928 (1993-12-01), Herh et al.
patent: 5270979 (1993-12-01), Harari et al.
patent: 5280198 (1994-01-
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