Processor

Details Processor Processor

2000-06-23

2004-06-29

Pan, Daniel H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Instruction modification based on condition

C712S024000, C712S217000, C712S219000, C712S221000, C712S043000, C712S223000, C711S125000, C711S172000, C708S501000

Reexamination Certificate

active

06757813

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a processor and more particularly to the processor capable of executing plural instructions simultaneously.
2. Description of the Related Art
Conventionally, various ideas are proposed for parallel processors executing plural instructions simultaneously to improve performance of processors.
One of the ideas, a VLIW (Very Long Instruction Word), has been proposed. In this idea, a program includes information indicating instructions which can be executed simultaneously, so as to reduce complications of instruction decoders. For example, a VLIW processor is explained in pages 18 through 21, MICROPROCESSOR REPORT Vol. 8, No. 2, Feb. 14, 1994.
In parallel processors executing plural instructions simultaneously, i.e., a VLIW processor, plural instructions to be executed simultaneously are processed independently. For example, Laid-open Japanese Patent Application No. Hei4-238537 shows in
FIG. 6
a processor that is independently prepared for each of the instructions simultaneously processed.
In this processor, when a register is designated as storage for plural operation results obtained by independent-plural processing units, conventionally, one of the following procedures is applied: one of the operation results is given top priority to be stored in the registers; and either another operation result is delayed from being written in the register or making codes designating the register in duplication is prohibited.
FIG. 14
shows registers into which operation results are written in a conventional parallel processor or a like processor executing plural instructions.
An instruction code
1
is decoded by a decoder
3
and drives processing unit
5
. Operation results of the processing unit
5
and a processing unit
6
are respectively selected by a selector
7
and a selector
8
and are respectively written in a register
9
and a register
10
.
In this case, when an operation result by the processing unit is designated to be written in the register
9
as a decoded result of the instruction code
1
by the decoder
3
, the selector
7
selects the operation result of the processing unit
5
.
Similarly, when an operation result by the processing unit
6
is designated to be written in the register
9
as a decoded result of an instruction code
2
by a decoder
4
, the selector
7
selects the operation result of the processing unit
6
. When two results are designated to be written in one register as the decoded results of the decoder
3
and the decoder
4
, for example, when both results are designated to be written in the register
9
, it is designed that only one of the results is written in the register
9
, or it is designed that neither results are written in the resister
9
.
FIG. 11
is a case in that the result of the processing unit
5
is written into the register
9
and the result of the processing unit
6
is written in the register
10
. In this case, writing destination registers are different.
FIG. 12
shows an action in the processor when writing-destination-registers are identical. In this case, priority is given to one result of the processing unit
5
or the processing unit
6
and only one result is written. In
FIG. 12
, the result of the processing unit
5
is written in the register
9
and the result of the processing unit
6
is discarded
FIG. 13
is a table showing example contents to be written in the registers
9
and the register
10
according to writing destination instructions of the instruction code
1
and the instruction code
2
. In this case, priority is given to result writing instructed by the instruction code
1
over result writing instructed by the instruction code
2
.
However, there are problems in the above-described conventional processor.
A first problem is that the use efficiency of the registers degrades.
To perform operation processes efficiently, in executing plural operations simultaneously, when one register is designated as operation result writing destinations, only one result is written, or, neither results are written. That is why it is necessary to describe codes in a manner such that the results of instructions to be executed simultaneously are written in respective registers. In this case, though a necessary bit-accuracy is smaller than a bit-width of a register (for example, smaller than half of the bit-width) and all operation results are stored in one register, an identical number of both registers and number of operations are required.
Another problem is that processing efficiency degrades.
When plural operation results written in plural registers are stored in a memory, it is necessary to store plural register contents in the memory. As a result, contents are stored in the memory with a memory storing instruction thereby increasing the number of instructions, and processing efficiency decreases.
SUMMARY OF THE INVENTION
In view of the above it is an object of the present invention to provide a processor capable of improving processing efficiency by increasing use efficiency of registers and thereby storage process to a memory decreases.
According to a first aspect of the present invention, there is provided a processor executing plural instructions simultaneously, wherein register numbers of the plural instructions to be executed simultaneously are compared, kinds of operations to be executed by the plural instructions are changed in response to a comparison result.
In the foregoing, a preferable mode is one wherein the register numbers to be compared are writing-destination-register numbers.
Also, a preferable mode is one wherein when the writing-destination-register numbers of the plural instructions to be executed simultaneously are identical, a constant operation is applied to plural operation results obtained from the plural instructions to obtain an operation result and the operation result is written into a writing-destination-register instructed by the plural instructions.
Also, a preferable mode is one wherein the operation result is obtained by concatenating plural parts of the plural operation results.
Also, a preferable mode is one wherein the operation result is obtained by rounding the plural operation results and concatenating plural parts of plural rounded operation results.
Also, a preferable mode is one wherein the operation result is obtained by adding the plural operation results.
Also, a preferable mode is one wherein the operation result is obtained by logical summing of the plural operation results.
Also, a preferable mode is one wherein the operation result is obtained by logical multiplying of the plural operation results.
With the above configuration, plural operation results outputted from plural processing units executing processes simultaneously are put together into one result and the result is stored in one register. Consequently, since a number of registers required to be stored with operation results decreases, a register use efficiency can be improved. Further, when results are written into a memory, a number of storing instructions can be reduced compared to plural values in registers. As a result, process efficiency can be improved.
According to a second aspect of the present invention, there is provided a processor executing plural instructions simultaneously, the processor including a comparison part for comparing register numbers of the plural instructions to be executed simultaneously, and a changing part for changing kinds of operations to be executed by the plural instructions in response to a comparison result of the comparison part.
In the foregoing second aspect, the comparison part may be a register check circuit, and the changing part may be a processing unit and/or a selector.


REFERENCES:
patent: 5404470 (1995-04-01), Miyake
patent: 5442581 (1995-08-01), Poland
patent: 5881307 (1999-03-01), Park et al.
patent: 04-109336 (1992-10-01), None
patent: 2874351 (1999-01-01), None
Gwennap, L., “VLIW: The Wave of the Future?”, Microprocessor Report, vol. 8, No. 2, Feb. 1994 pps 1

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