Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2002-11-13
2004-11-23
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S081000, C326S119000, C326S121000, C326S063000, C327S333000, C327S427000
Reexamination Certificate
active
06822479
ABSTRACT:
FIELD OF THE INVENTION
The present invention is generally directed to an integrated circuit and method of operation thereof, and is more preferably directed to an input/output buffer of an integrated circuit and method of operation thereof. Even more preferably, it is directed to power up sequence indifferent I/O buffers.
BACKGROUND OF THE INVENTION
An integrated circuit typically receives supply voltage in the form of a core voltage (such as a voltage of about 1.5 volts, for example) for supplying core power to an integrated circuit chip, and an input/output (I/O) power voltage (such as a voltage of about 2.5 volts, for example) for supplying I/O power to various drivers and input/output functions of the integrated circuit including, but not limited to, input/output buffers of the integrated circuit. Based on timing of the I/O voltage and the core voltage to the integrated circuit, problems can occur.
A driver in one integrated circuit typically drives other integrated circuits. Under power up conditions, integrated circuits and circuits within the integrated circuits could be contending with one other. Such contention consumes power and could cause integrated circuits to be damaged and burned. If there are multiple drivers, the power supply of an entire mother board may short circuit or a fuse may burn.
A typical circuit for an I/O buffer of an integrated circuit is shown in FIG.
1
. Such a circuit will cause contention when powered up, unless additional measures are taken. These measures will require additional circuits and signals.
The core power logic portion of the circuit typically includes a pair of non-complex inverters
106
and
112
, each of which receives the input core voltage. The I/O power logic portion of the circuit typically includes a level shifter at the front end of an I/O buffer and a second input/output buffer portion
150
(such as an output buffer, for example), wherein the level shifter may include a pair of cross coupled inverters
120
and
130
, and additional pull down transistors
108
and
114
.
The inverters each receive the I/O supply voltage as indicated by elements
122
and
132
, and each may include a P-channel transistor
124
,
134
, and an N-channel transistor
126
and
136
. Preferably, the additional transistors
108
and
114
are also N-channel transistors.
The circuit is typically configured such that the output of the first P-channel transistor
124
connects to the input of the second P-channel transistor
134
and the second N-channel transistor
136
, with the output of the second P-channel transistor
134
being connected to the input of the P-channel transistor
124
and the N-channel transistor
126
. The output of the first P-channel transistor
124
also provides an input to the second I/O buffer portion
150
, either providing activation of various drivers and circuits of the I/O buffer (in this exemplary case, in an active low condition), or providing a signal which does not activate the second I/O portion
150
. Each of the N-channel transistors
114
and
108
are preferably grounded at elements
110
and
112
; and each of the N-channel transistors
126
and
136
are preferably grounded at elements
128
and
138
.
The circuits shown in
FIG. 1
each include inverters with a P-channel transistor acting as a pull-up transistor and an N-channel transistor acting as a pull-down transistor. Due to the presence of the cross coupled inverters, one N-channel transistor is on and thus pulls down, and the other N-channel transistor is off, and thus the other P-channel transistor pulls up. There is some contention between the transistors until the second P-channel transistor
134
feeds its input to the first P-channel transistor
124
to essentially turn it off and allow that P-channel transistor
124
to give into the pull-down of the N-channel transistor
126
. This momentary contention typically arises for a time on the order of a one inverter delay.
At a time when no core power is being supplied, however, both additional pull down N-channel transistors
114
and
108
are off, and thus both N-channel transistors
126
and
136
do not want to pull down. When the I/O voltage is then supplied at
122
and
132
in the absence of core power, none of the N-channel transistors want to pull down and the two cross coupled inverters
120
and
130
wake up in an unpredictable state. If the inverter
120
wakes up low and outputs an active low signal to the second I/O buffer portion
150
, the output drivers of the second I/O buffer portion
150
wake up active and may begin to drive something. This I/O circuit could be connected to another I/O circuit which also may wake up in an active state and thus two integrated circuits may begin driving, and contention may result.
Similarly, if the I/O power is supplied before the core power in such a circuit, additional contention problems could occur. Thus, some suppliers have tried to advise that core power be supplied within 20 milliseconds, for example, of I/O power, in an attempt to limit any damage of contention. It is very difficult to meet such a demand, and such contention could violate component specifications.
SUMMARY OF THE INVENTION
The present invention, in one preferred embodiment, is directed to an integrated circuit including at least one I/O buffer. This buffer includes a first supply logic portion, connectable to a core voltage supply and an I/O voltage supply, and a second I/O buffer portion adapted to receive an activation signal from the first supply logic portion. The first supply logic portion is modified to prevent the output of the activation signal until the core voltage is supplied to the integrated circuit.
In such a preferred embodiment, the second
116
portion buffer will power up (from the
110
domain supply) in a “not active” state in the absence of core power. Thus, the integrated circuit can tolerate a long and potentially indefinite interval of time between the application of I/O power and the application of core power.
In another embodiment, the invention is directed to a method of operation of an integrated circuit including at least one input/output (I/O) buffer including, the buffer further including an input/output buffer portion adapted to become active upon receiving an activation signal and a supply logic portion connectable to a source adapted to supply a core voltage and a source adapted to supply an input/output (I/O) voltage. The method includes preventing the input/output buffer portion from being activated until the core voltage is supplied to the integrated circuit, and buffering information in the input/output buffer portion.
REFERENCES:
patent: 5737612 (1998-04-01), Ansel et al.
patent: 6237103 (2001-05-01), Lam et al.
patent: 6342802 (2002-01-01), Forehand
patent: 6614283 (2003-09-01), Wright et al.
Marvell Semiconductor Israel Ltd.
Tan Vibol
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