Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2003-08-21
2004-12-21
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S693000, C257S706000, C257S783000, C257S787000
Reexamination Certificate
active
06833614
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package and a semiconductor device and, more particularly, a semiconductor package of FBGA (Fine Pitch Ball Grid Array) type, or the like employed in the high frequency application, and a semiconductor device in which a semiconductor chip is packaged in the semiconductor package.
2. Description of the Related Art
In recent years, in the high-frequency application semiconductor device employed in the telecommunication apparatus, etc., the signal speed is being increased highly, and such higher speed of the signal is restricted by the disturbance in the signal waveform. For this reason, the semiconductor device that can suppress the disturbance in the signal waveform even when the higher speed signal is applied is desired. Such semiconductor device has the FBGA type structure using two metal wiring substrates, for example.
FIG. 1
is a sectional view showing a semiconductor device having the FBGA type structure in the related art, and
FIG. 2
is partial plan view viewed from an A portion in FIG.
1
.
As shown in
FIG. 1
, in a semiconductor device
120
of the FBGA package type in the related art, signal wiring layers
102
are formed on one surface of an insulating film
100
, and a ground plane
104
is formed on the other surface to spread over the entire surface. The signal wiring layers
102
are covered with a solder resist film
106
except their bump connection portions. In this manner, a wiring substrate
105
is basically constructed. Then, solder balls
108
are mounted on the bump connection portions of the signal wiring layers
102
respectively.
A surface of the wiring substrate
105
on the ground plane
104
side is adhered to a peripheral portion of a stiffener
112
(radiating plate and reinforcing plate), to a center portion of which a cavity
112
a
is provided, via an adhesive layer
110
so as to avoid the cavity
112
a
. Also, the back surface side of a semiconductor chip
114
having connection electrodes
114
a
thereon is adhered to a bottom portion of the cavity
112
a
of the stiffener
112
by die bonding material
110
a.
The connection electrodes
114
a
of the semiconductor chip
114
and wire bonding pads
102
a
of the signal wiring layers
102
on the wiring substrate
105
are connected via wires
116
. In addition, the semiconductor chip
114
, the wires
116
, and the wire bonding pads
102
a
of the signal wiring layers
102
are sealed by a sealing resin
118
.
Also, as shown in
FIG. 2
, if the signal wiring layers
102
in
FIG. 1
are viewed from the A portion, the signal wiring layer
102
consists of a wiring line portion
102
x
and a connection pad portion
102
y
. The wiring line portion
102
x
is formed to have an almost identical wiring width over the entire transmission path. While, a diameter of the connection pad portion
102
y
is formed thicker than the wiring width of the wiring line portion
102
x
because the solder ball
108
having a relatively large diameter is placed on the connection pad portion
102
y.
In addition, ground wiring layers
103
are formed adjacently on both sides of plural signal wiring layers
102
. The ground wiring layers
103
are connected electrically to the ground plane
104
via through holes
100
a
. As described above, the semiconductor device
120
having the FBGA package structure in the related art is basically constructed.
In the wiring substrate
105
of the above semiconductor device
120
, it is possible to design the wiring line portion
102
x
of the signal wiring layer
102
such that, if the wiring width of the wiring line portion
102
x
is arranged to have the almost identical width over the overall transmission path, the electrostatic capacity between the wiring line portion
102
x
and the ground plane
104
, etc. can be set almost identically.
In addition, the ground wiring layers
103
can be arranged near the signal wiring layer
102
in such a manner that space portions are set almost equal. In this fashion, since the impedance matching can be implemented in the wiring line portion
102
x
, a transfer loss of the signal is seldom generated.
However, because the solder ball
108
is mounted on the connection pad portion
102
y
, the connection pad portion
102
y
of the signal wiring layer
102
is arranged to have a larger width than the wiring width of the wiring line portion
102
x
. Therefore, the electrostatic capacity between the wiring line portion
102
x
and the ground plane
104
becomes different from the electrostatic capacity between the connection pad portion
102
y
and the ground plane
104
, so that the impedance matching is largely lost. As a result, there is such a problem that the transfer loss of the signal is generated and thus the transfer characteristic at a desired frequency cannot be obtained.
Also, in the case that the conventional semiconductor device
120
is packaged in the packaging substrate, if the stress is applied to the semiconductor device
120
from the horizontal direction, such stress is concentrated to jointed portions of the solder balls
108
in the semiconductor device
120
. Thus, it is possible that the signal wiring layers
102
jointed to the solder balls
108
, etc. are disconnected.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor package that can cause the overall transmission path to match the impedance and also generates no trouble when stress is applied on packaging such package in a packaging substrate, and a semiconductor device in which a semiconductor chip is packaged in the semiconductor package.
The present invention provides a semiconductor package which comprises a metal plate; and a wiring substrate having an insulating substrate, signal wiring layer formed on one surface of the insulating substrate, and a ground plane formed integrally on other surface of the insulating substrate, whereby a surface of the wiring substrate on a ground plane side is adhered onto the metal plate; wherein the signal wiring layer is constructed by a wiring line portion and a connection pad portion whose width is thicker than a width of the wiring line portion, and a non-forming portion is provided in portion of the ground plane, which corresponds to the connection pad portion.
In the present invention, in order to attain the impedance matching between the wiring line portion of the signal wiring layer and the connection pad portion whose width is larger than that of the wiring line portion, the non-forming portion is provided by removing from a portion of the ground plane, which corresponds to the connection pad portion.
In one preferred embodiment of the present invention, the metal plate and the wiring substrate are adhered mutually by the resin layer. The non-forming portion of the ground plane may be formed as a hollow, or may be filled with the resin layer respectively. Otherwise, the non-forming portion of the ground plane may be formed as a hollow, and a resin layer may be interposed between the non-forming portion and the metal plate.
The electrostatic capacity, which is formed between the wiring line portion and the ground plane, and the electrostatic capacity, which is formed between the connection pad portion and the metal plate, are made equal by adjusting a thickness of the non-forming portion of the ground plane, a thickness of the resin layer, or both thicknesses. According to this, the impedance matching is obtained between the wiring line portion and the connection pad portion.
Also, in one preferred embodiment of the present invention, a recess portion may be further provided in a portion of the metal plate corresponding to the non-forming portion of the ground plane. In this case, a depth of the recess portion is set to attain the impedance matching between the wiring line portion and the connection pad portion.
Also, in the wiring substrate that is adhered to the metal plate not to provide the ground plane on the other surface of the insulating substrate, similarly
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