Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2001-11-13
2004-02-24
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S780000, C257S772000, C257S779000, C257S750000, C257S737000
Reexamination Certificate
active
06696763
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90107846, filed on Apr. 2, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to an integrated circuit, and more particularly, to a solder ball allocation and a method for allocating the solder balls.
2. Description of the Related Art
A normal personal computer system is basically an assembly of a motherboard, an interface card and a peripheral; the motherboard is the base of the computer system. The motherboard comprises a central processing unit (CPU), several memory module slots, slots for installing the interface cards and a control chip set.
As semiconductor technique becomes increasingly advanced, chip operation is more powerful, and the integral functions thereof are also multiplied. The grid array package (GA) is one of the commonly used packages.
In early computers, the integral functions of the chip were small and slow, so that fewer voltage sources were required. The division of the power source block on the chip was easily formed without affecting the stability of the chip. In the current technique, as many functions and circuits, previously controlled and managed externally, have been integrated into one chip, the variety of the power source is increased. That is, the chip requires various voltage sources and more power source blocks to provide various voltages. As the chip is designed with increasing delicacy, residual space is reduced. The circuit layout cannot reach each region.
FIG. 2
shows a conventional through hole location. The power source blocks VCC
3
50
,
72
belong to the same voltage source and are connected with each other. Due to the existence of the through holes
54
and
56
in between, a fine wire is used to go through the through holes
54
and
56
, or connected externally the power source blocks VCC
3
50
and
72
. The very fine wire is a poor conductor and is easily broken to cause chip damage. If the external wiring is adopted, the wiring distances for the power source blocks VCC
3
50
and
72
are different to cause a voltage difference that affects the stability of the chip.
SUMMARY OF THE INVENTION
As a small volume and powerful functions become the leading trends of the industry, a solder ball allocation and a method thereof have to be developed to obtain a better performance and a more stable operation for the chip in the same environment. The Chinese patent application number 90100703 that increases the area of the ground plane is incorporated as a reference of the invention.
The invention provides a solder ball allocation and a method thereof Without increasing the chip area, the chip volume and the cost, the chip can be divided into various power source blocks.
For the solder ball allocation, the chip comprises a substrate, several first solder balls and second solder balls. The first solder balls are located in the periphery of the substrate. The first solder balls are spaced from each other by a first distance and arranged outwardly. The second solder balls are used to connect external devices. The second solder balls are located in a central part of the substrate and spaced from each other by a second distance. The second solder balls are arranged with several first geometric patterns that further construct a second geometric pattern with the center of the substrate as a center thereof. The distance from the center of the substrate to the corresponding point of the first geometric patterns is the same. The first solder region is spaced from the second solder region by a third distance, which is larger than the first and the second distance.
The above chip includes a ball grid array (BGA) packaged chip. The first and second solder balls are used for signal and ground connection. There are thirty two second solder balls. The second solder balls help the heat dissipation of the chip. The first geometric patterns and the second geometric pattern include rectangular patterns.
The invention provides a method of solder ball allocation on a chip. The chip comprises a substrate and several second solder balls for external connection. The second solder balls are located at a central part of the substrate, and the second solder balls are equidistant from each other and arranged outwardly. The chip is divided into various power source blocks. The conflicts between the second solder balls and the power source blocks are analyzed. The second solder balls having conflicts with the power source blocks are removed. The removed solder balls can be shifted to other locations on the chip.
The invention further provides a solder ball allocation on a chip. The chip comprises a substrate, several first solder balls for external connection and several second solder balls for external connection. The first solder balls are located in the periphery of the substrate. Each of the first solder balls is spaced from a neighboring first solder ball thereof by a first distance. The first solder balls are arranged outwardly. The second solder balls are located on a central part of the substrate and are equidistant from each other by a second distance. The second solder balls are arranged as a hollow geometric pattern with a center of the substrate as the center thereof The first solder balls and the second solder balls are spaced by a third distance. The third distance is larger than the first and the second distances.
The above chip includes a ball grid array packaged chip. The first and second solder balls are used for signal and ground connections. There are thirty two second solder balls. The second solder balls help the heat dissipation of the chip. The hollow geometric pattern includes a hollow rectangular pattern.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 4420203 (1983-12-01), Aug et al.
patent: 5770889 (1998-06-01), Rostoker et al.
patent: 5877553 (1999-03-01), Nakayama et al.
patent: 6444563 (2002-09-01), Potter et al.
patent: 6452262 (2002-09-01), Juneja
patent: 6498055 (2002-12-01), Fukuda et al.
patent: 6512680 (2003-01-01), Harada et al.
patent: 6562661 (2003-05-01), Grigg
Chen Hsiu-Tzu
Chen Shu-Hui
J.C. Patents
Luu Chuong A
Smith Matthew
Via Technologies Inc.
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