Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2001-01-26
2004-10-26
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
Reexamination Certificate
active
06810482
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electronic integrated circuit design. More particularly, the present invention relates to a system and method for estimating power consumption and energy dissipation in an integrated circuit (IC) at the register transfer level (RTL), behavioral level and system level.
BACKGROUND OF THE INVENTION
Electronic systems and circuits have made a significant contribution towards the advancement of modem society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Electronic systems designed to provide these benefits include integrated circuits (ICs) that consume power. Power consumption typically has a significant impact on the operations of an IC and accurate modeling techniques are usually critical to design processes.
The complexity of commonly used integrated circuits has advanced dramatically and design efforts usually require the assistance of computer aided design (CAD) tools. The automated development of complex integrated circuits such as application specific integrated circuits (ASICs) is referred to as electronic design automation (EDA). EDA tools are usually software programs that provide instructions to a computer for processing information associated with a circuit design. Usually, input information for an EDA tool conforms to a description language such as Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), Verilog or C programming language and describes the functional attributes of a circuit. The description language files facilitate manipulation and design of IC components by an EDA tool across varying levels of abstraction from functional operation to physical structure. Designs are typically described in functional terms at a register transfer level (RTL), behavioral level or system level in VHDL, Verilog or C code which an EDA tool converts into a structural design of elements or circuits and from that point a gate level compilation is performed.
Designs typically evolve through different level of abstractions that provide different advantages in the design process. Most designs start with a system level description and that is converted into a RTL description in a description language like VHDL by EDA tools. The RTL description is converted into a gate level description by the CAE tools focusing on logic synthesis. The translation of RTL description into a gate level description is resource (e.g., labor) intensive process. Changes in the design usually require a re-write of the RTL description and reprocessing of the synthesis process.
A number of time consuming and resource intensive CAD techniques have been proposed for gate-level power estimation. EDA input manipulation is significantly easier at a functional design level but a design is not typically final when a functional description is written. Depending on the working attributes of the design, the size or bit widths of component selections by the synthesis process may vary and when synthesis is performed there may be a requirement to change the size of a component (e.g., a 6 bit adder, an 8 bit adder or a 32 bit adder, etc.). Although CAE design tools typically provide some assistance to engineers in designing and analyzing circuits, a sizable amount of valuable resources are expended interfacing with the CAE tools and after a design is specified at the gate level it is usually relatively expensive to make adjustments. One of the most significant challenges in modem circuit design is getting an accurate and reliable estimation of power consumption at an early point in the design process or at a convenient level of design abstraction such as the RTL, behavioral level and system level.
Designing complex electronic systems and circuits usually requires arduous analysis of numerous electrical characteristics, including power consumption and heat dissipation. Typically, it is important for a circuit design to provide for efficient energy use and power conservation. For example, portable electronic devices usually have limited power supplies and accurately estimating power consumption is particularly important. Estimating power consumption typically requires extensive calculations and manipulation of complicated electrical principles of physics. The analysis becomes even more complex when designers attempt to integrate numerous electronic components on a single integrated circuit chip, giving rise to a variety of factors requiring careful review and attention. For example, energy is usually dissipated as heat when the electronic system is performing certain functions and if IC components get overheated they usually stop operating properly and do not produce desired results. As the placement of transistors and other components in an IC becomes denser, heat dissipation concerns become compounded by the closeness of the components to one another. Despite design complications, densely placing components in an IC typically provides significant benefits such as increased functionality and reductions in size which enables greater portability.
Power is usually consumed by an complementary metal oxide semiconductor (CMOS) integrated circuit during operation cycles such as switching operations of a transistor. Typically, power is consumed and energy is dissipated as heat when the input and output logic values of combinational circuits toggle (e.g., when transistors of a logic gate engage in a switching activity). Some traditional power consumption modeling approaches attempt to capture the dependence of combinational IC power consumption on input and output activity (e.g., toggle events). One such approach involves power macromodels of three dimensional tables described in “Power Macromodeling for High Level Power Estimation” by Subodh Gupta and Farid Najm for DAC 97. It is often relatively expensive to create three dimensional table power macromodels for a particular circuit block and creating one for each possible circuit block that may be included in an IC usually requires expenditure of significant resources. Different target technologies usually have different power dissipation and require dedicated characterization runs.
ASIC chips typically include various functional components that are coupled together and to Input/Output (IO) cells. These functional components often have a similar architecture characteristics and features. For example, there are a number of functional components such as adders or multipliers that are made up of similar repetitive building block circuits. The functional components often have dimensional associations between inputs, for example some functional components have symmetrical inputs (e.g., a 4 by 4 adder, or an 8 by 8 adder, etc.). Functional components with similar architectures and input associations often have power consumption tendencies that are relatively scaleable and lend themselves to extrapolation based power consumption estimates. However, recent attempts at providing accurate abstract level (e.g., RTL) power consumption estimates for scaleable circuits are often relatively inaccurate and unreliable.
Some scaleable power consumption estimation approaches utilize constant multipliers such as those described in “Parameterzable RTL Power Models for Combinational Soft Macros” written by Bogliolo et al for ICCAD 99. Traditional constant multiplier approaches require power consumption characterization for a selected bit width and power consumption characteristics of other bit widths are calculated by multiplying the power characteristics of the selected bit width by a constant value. These prior constant multiplier approaches often lack sufficient accuracy since they do not account for a number of factors that affect power consumption. Circuits toggling at a rat
Mehra Renu
Saxena Vikram
Bever Hoffman & Harms LLP
Connolly Mark
Harms Jeanette S.
Synopsys Inc.
LandOfFree
System and method for estimating power consumption of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for estimating power consumption of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for estimating power consumption of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3294600