Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-01-24
2004-03-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S321000, C257S339000
Reexamination Certificate
active
06710396
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a split-gate flash memory cell and its flash memory array and, more particularly, to a self-aligned split-gate flash cell structure having a ridge-shaped floating-gate layer and its contactless flash memory arrays.
DESCRIPTION OF THE RELATED ART
A split-gate flash cell structure having a select-gate region and a floating-gate region offers in general a larger cell size as compared to that of a stack-gate cell structure and is usually configured to be a NOR-type flash memory array.
FIG. 1
shows a conventional split-gate flash memory device having a floating-gate layer
211
formed by a local oxidation of silicon (LOCOS) technique, in which the floating-gate length is defined in general to be larger than a minimum feature size (F) of technology used due to a bird's beak formation; a control-gate layer
215
is formed over a LOCOS-oxide layer
212
and a thicker select-gate oxide layer
214
; a poly-oxide layer
213
is formed over a sidewall of the floating-gate layer
211
; a source diffusion region
216
and a drain diffusion region
217
are formed in a semiconductor substrate
200
in a self-aligned manier, and a thin gate-oxide layer
210
is formed under the floating-gate layer
211
. The split-gate flash cell structure shown in
FIG. 1
is programmed by mid-channel hot-electron injection, the programming efficiency is high and the programming power is low as compared to channel hot-electron injection (CHEI) used in a stack-gate flash cell structure. Moreover, the over-erase problem of the split-gate flash cell structure can be prevented due to a high threshold-voltage for the select-gate region, so the control logic circuits for erasing and verification can be simplified. However, there are several drawbacks for FIG.
1
: the cell size is much larger due to the non-self-aligned control-gate structure; the control-gate length can't be easily scaled down due to the misalignment of the control-gate layer
215
with respect to the floating-gate layer
211
; the coupling ratio is low and a higher applied control-gate voltage is required for erase; the field-emission tip of the floating-gate layer
211
is difficult to be controlled due to the weak masking ability of the bird-beak oxide; and a high temperature process is required to form a thicker LOCOS-oxide layer
212
in order to obtain an appreciate tip.
It is therefore a major objective of the present invention to provide a simple low-temperature process for forming a ridge-shaped floating-gate layer for a self-aligned split-gate flash cell structure with a higher field-emission efficiency.
It is another objective of the present invention to provide a self-aligned split-gate flash cell structure having a scalable cell size equal to or smaller than 4F
2
.
It is a further objective of the present invention to provide a higher coupling ratio for a self-aligned split-gate flash cell structure.
It is yet another objective of the present invention to provide two contactless architectures for self-aligned split-gate flash memory arrays.
Other objectives and advantages of the present invention will be more apparent from the following description.
SUMMARY OF THE INVENTION
A self-aligned split-gate flash cell structure of the present invention is formed on a semiconductor substrate of a first conductivity type having an active region isolated by two parallel shallow trench isolation (STI) regions. A cell region can be divided into three regions: a common-source region, a self-aligned split-gate region, and a common-drain region, wherein the self-aligned split-gate region is located between the common-source region and the common-drain region. The common-source region comprises a first sidewall dielectric spacer being formed over a first sidewall of the self-aligned split-gate region and on a portion of a first flat bed being formed by a common-source diffusion region of a second conductivity type in the active region and two third raised field-oxide layers in the two parallel STI regions. The common-drain region comprises a second sidewall dielectric spacer being formed over a second sidewall of the self-aligned split-gate region and on a portion of a second flat bed being formed by a common-drain diffusion region of the second conductivity type in the active region and two fifth raised field-oxide layers in the two parallel STI regions. The self-aligned split-gate region comprises a ridge-shaped floating-gate structure being formed on a first gate dielectric layer in a floating-gate region with a first intergate dielectric layer being formed on its top portion and a second intergate dielectric layer being formed on its inner sidewall; and a control/select-gate conductive layer being formed at least over a second gate dielectric layer in the select-gate region and the first/second intergate dielectric layers in the floating-gate region and a portion of the first raised/planarized field-oxide layers in the two parallel STI regions, wherein the ridge-shaped floating-gate layer is formed by anisotropic dry etching to have a single-side tapered structure and its ridge-shaped tip is defined by a buffer sidewall dielectric spacer.
The self-aligned split-gate flash cell structure of the present invention as described is used to implement two contactless flash memory array architectures: a contactless NOR-type flash memory array and a contactless parallel common-source/drain conductive bit-lines flash memory array. The contactless NOR-type flash memory array comprises a plurality of common-source conductive bus lines being formed alternately in the common-source regions and transversely to a plurality of active regions and a plurality of parallel STI regions; a plurality of common-drain conductive islands being at least formed over the plurality of active regions along each of the common-drain regions and being located between the plurality of common-source conductive bus lines; a plurality of self-aligned split-gate flash cell structures being formed between each of the plurality of common-source conductive bus lines and its nearby common-drain conductive islands with the control/select-gate conductive layer being acted as a word line; and a plurality of metal bit-lines integrated with the plurality of common-drain conductive islands being simultaneously patterned and etched by using a plurality of hard masking layers. Each of the plurality of hard masking layers includes a masking dielectric layer being aligned to each of the active regions and a sidewall dielectric spacer being formed over each sidewall of the masking dielectric layers.
The contactless parallel common-source/drain conductive bit-lines flash memory array of the present invention comprises a plurality of common-source conductive bit lines and a plurality of common drain conductive bit lines being formed alternately and transversely to a plurality of active regions and a plurality of parallel STI regions; a plurality of self-aligned split-gate flash cell structure being formed between each of the plurality of common-source conductive bit lines and each of the plurality of common-drain conductive bit lines; and a plurality of metal word lines integrated with a plurality of planarized control/select-gate conductive islands being simultaneously patterned and etched to be perpendicular to the plurality of common-source/drain conductive bit lines by using a plurality of hard masking layers. Each of the plurality of hard masking layers includes a masking dielectric layer being aligned to each of the active regions and a sidewall dielectric spacer being formed over each sidewall of the masking dielectric layers.
REFERENCES:
patent: 6433384 (2002-08-01), Hashimoto
patent: 6436764 (2002-08-01), Hsieh
patent: 6462375 (2002-10-01), Wu
patent: 6531734 (2003-03-01), Wu
patent: 6570231 (2003-05-01), Yasumi et al.
Nelms David
Nguyen Dao H
Pro-Techtor Inter-national Services
Silicon-Based Technology Corp.
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