Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2002-09-27
2004-11-09
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S685000, C257S686000, C257S777000, C257S723000
Reexamination Certificate
active
06815832
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device having a chip-on-chip structure having a semiconductor chip superposed with another semiconductor chip thereon.
2. Description of Related Art
There is a chip-on-chip structure having a pair of semiconductor chips connected together by being opposed at their active surfaces, as one form of a multi-chip semiconductor device having a plurality of semiconductor chips connected with one another to be molded with a resin. In the semiconductor device of such a structure, a pair of semiconductor chips formed with internal connection electrodes in the active surfaces are opposed at their active surfaces and connected together by being aligned on the active surface such that the corresponding ones of internal connection electrodes are connected (internally connected) together.
The internal connection electrodes are formed as bumps projecting from the active surface. The internal connection electrodes, however, have deviations in height. Consequently, when the semiconductor chips at the active surfaces are opposed in parallel with each other, the corresponding internal connection electrodes in each set are not constant in the sum of their heights. For this reason, the internal connection electrodes have a narrow spacing in a set having a greater height sum while the internal connection electrodes have abroad spacing in a set having a smaller height sum. During interconnecting the internal connection electrodes, by crushing under pressure the internal connection electrodes of the set greater in height sum, mutual connection is provided on all the internal connection electrodes including the internal connection electrodes smaller in height sum.
External extension electrodes are provided on one of a pair of semiconductor chips to be connected chip on chip. The external extension electrodes are connected to an external connection member, such as a leadframe. Through the external connection member, the semiconductor device can be connected to another circuit board. In the case internal connection is properly done, a predetermined input/output characteristic is obtained through the external connection member as terminals.
A multiplicity of internal connection electrodes are provided on each semiconductor chip. Unless interconnections are all proper on the corresponding internal connection electrodes, the semiconductor device cannot have a predetermined input/output characteristic hence resulting in the unacceptable product. Confirming an internal connection state is made not only on a completed semiconductor device but also as an intermediate test in the manufacturing process. In the intermediate test, electric characteristics are measured through the external extension electrodes in order to confirm a normality/abnormality of internal connection. Namely, a probe for electrical-characteristic measurement is put on every external extension electrode to examine whether a desired input/output characteristic is available or not. Besides, measurement is made for a conduction at between the external extension electrodes in a particular set.
However, despite electrical connection is made between all the corresponding ones of the internal connection electrodes, there are cases that junction is provided between the internal connection electrodes with a deviation on the active surface from a predetermined relative position. In such a case, junction area is smaller as compared to the case where connection is made in a predetermined relative position between the internal connection electrodes. This reduces the mechanical strength at the junctions, resulting in a fear of a fracture at the junctions even under an application of slight loading. Consequently, the semiconductor device having such junctions between the internal connection electrodes should be determined unacceptable.
However, even in such a case, determination is frequently made as proper in the conventional electrical-method test. This is because a rise in electrical resistance is not to be recognized unless the junction area is decreased between the internal connection electrodes to a considerable extent. It is impossible to determine a size of an junction area in the electrical test.
Meanwhile, even where alignment is accurately done on the active surface, when connection is made between the internal connection electrodes under pressurization or the like, there is a decrease in junction area on the internal connection electrodes in a set having a small height sum. In case there are a number of internal connection electrodes small in junction area, there is a possibility not to provide a junction with sufficient strength at between semiconductor chips through internal connection electrodes. In such a case, junction normality/abnormality cannot be determined in the conventional test method.
Furthermore, poor internal connection, in many cases, results from nonparallel arrangement at the active surfaces of a pair of semiconductor chips to be mutually connected. In such a case, the above frequently causes non-connection at between the internal connection electrodes or unstable connection thereof, in a region the spacing is great between the active surfaces. For such a simple cause of poor connection, the conventional semiconductor device must be examined for a conduction and input/output characteristic by putting a probe on every external extension electrode, thus requiring time and cost upon testing.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of determining whether internal connection has been properly done or not.
Also, another object of the invention is to provide a semiconductor device capable of simply determining a normality/abnormality of internal connection.
A semiconductor device according to one aspect of the invention comprises a first semiconductor chip having, on an active surface, a first internal connection electrode and a first lateral-deviation confirming electrode and a second semiconductor chip having, on an active surface, a second internal connection electrode corresponding to the first internal connection electrode and a second lateral-deviation confirming electrode corresponding to the first lateral-deviation confirming electrode, that are connected opposed at the respective active surfaces. The first lateral-deviation confirming electrode and the second lateral-deviation confirming electrode are arranged in such positions that mutual connection is made when the first internal connection electrode and the second internal connection electrode are connected together in a predetermined relative position in an on-plane direction of the active surface but mutual connection is not made when the first internal connection electrode and the second internal connection electrode deviate by a constant distance or greater in a predetermined lateral-deviation detecting direction on a plane of the active surface within a range to keep mutual connection thereof.
The internal connection electrode and the lateral-deviation confirming electrode may be in a projection (bump) form projecting from the active surface.
According to the invention, even where all the corresponding first and second internal connection electrodes are electrically connected together, when these are connected with a deviation by a predetermined distance or greater in a predetermined lateral-deviation detecting direction from a predetermined relative position on the active plane, connection is not made between the first and second lateral-deviation confirming electrodes. Accordingly, in the case where no electrical conduction is available at between the first and second lateral-deviation confirming electrodes, it is possible to determine that the first and second internal connection electrodes are deviated by a predetermined distance or greater from the predetermined relative position in an on-plane direction of the active surface.
In such a case, the corresponding first and second internal connection el
Nguyen DiLinh
Pham Long
Rabin & Berdo P.C.
Rohm & Co., Ltd.
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