Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data... – Inhibiting timing generator or component
Reexamination Certificate
2000-08-11
2004-08-24
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
Inhibiting timing generator or component
C713S322000
Reexamination Certificate
active
06782486
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer systems and, more particularly, to clock forwarded subsystems and power management.
2. Description of the Related Art
A computer system typically includes at least one processor (also referred to as a “microprocessor”) that typically performs processing of a number of instructions from one or more programs or applications under execution. As part of its processing operations, the processor may need to access a number of system buses for required data transfer. For example, a multimedia application may require the processor to transfer certain data to a separate video processor and retrieve the processed information from the video processor through a dedicated video bus. Further, the processor may communicate with one or more I/O devices through a separate I/O bus, and with one or more system memories through a dedicated memory bus. Additional buses may be present in the computer system based on the system device complexity and the level of interconnection among various electronic devices constituting the computer system.
The computer system may also include a bus bridge to effectively manage the binary information traffic between the processor and one or more system buses. The bus bridge may also facilitate cache coherent data transfers within the system in view of the possibility of independent memory accesses by the processor and one or more I/O devices. Various system components may be coupled to the processor via the bus bridge. In other words, the bus bridge may be directly connected to the processor, and, hence, may directly receive all address and data information from the processor. The bus bridge may, in turn, distribute the received information to appropriate system devices via appropriate system buses. Similarly, information received from one or more system devices over different system buses may be routed to the processor via the bus bridge in a systematic manner.
To systematically exchange data between two devices, the devices may be connected via a clock forwarded interface for high bandwidth data transfers. A clock forwarded interface accomplishes point-to-point transfers of binary information by having the sender provide the receiver with a forward clock that latches the transmitted data at the receiver. The receiver may then sample the received binary information using its internal clock. The sender synchronizes the address and/or data transmitted by the sender to the forward clock.
A typical semiconductor device dissipates electrical power (i.e., transforms electrical energy into heat energy) during operation. The electrical power dissipated by a semiconductor device is proportional to the speed (or frequency) at which that semiconductor device operates during run-time. The higher the operating frequency of the semiconductor device, the greater the generation of heat energy by the semiconductor device. In applications where power requirements are critical, unnecessary power consumption may not be tolerable. Therefore, some devices may go into an idle state to reduce power consumption.
Additionally, the amount of noise that is generated by a semiconductor device is proportional to the amount of digital logic that is switching at any point in time. In order to reduce noise and power consumption in a clock forwarded I/O device, the transmitting clock may be turned off once the data has been latched at the receiver. The receiver of the device will continue to process the received data after the forward clock has stopped. In some cases, the receiver logic clock may continue to run even after there is no data to receive in order to maintain synchronicity when the sender begins transmitting data and a forward clock.
In a clock forwarded I/O device, it is desirable that the receiving device be allowed to enter a low power state when there is no data to process. It may therefore be desirable to allow the receiver to enter and exit its low power state while also ensuring the requisite synchronism between the forward clock from the sender and the internal receive logic clock of the receiver.
SUMMARY OF THE INVENTION
The problems outlined above may in large part be solved by an efficient clock stop and start apparatus for clock forwarded system I/O. In one embodiment, the apparatus may include a buffer coupled to receive incoming data from a data source. The buffer is clocked by a first clock signal that is provided by the data source. The buffer is configured to store the incoming data in a plurality of sequential lines in response to the first clock signal. The buffer may be further configured to store a plurality of bits in a plurality of occupied-bit registers. Each one of the plurality of occupied-bit registers indicates that data is present in a corresponding sequential line in the buffer.
The apparatus may further include a clock gate circuit coupled to the buffer and configured to provide a second clock signal. The clock gate circuit may be further configured to start the second clock signal when valid data is present in the buffer and to stop the second clock signal when no data is present in the buffer.
In other embodiments, the apparatus may include a plurality of synchronizers, which are coupled to the buffer. Each one of the plurality of synchronizers may be configured to latch the output of a corresponding one of the plurality of occupied-bit registers. Each one of the plurality of occupied-bit registers may be further configured to reset after the data present in a corresponding sequential line in the buffer has been accessed and in response to receiving a valid reset signal.
The apparatus described above may advantageously reduce power consumption and noise of a device by allowing a device that is receiving data in a clock forwarded I/O system to shut off its internal receiving logic clock when there is no data to process. Furthermore, the apparatus may also allow a device that is receiving data in a clock forwarded I/O system to start its internal receiving logic clock when data is received and is ready to be processed.
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“Gated Clock Removal Algorithm”, IBM Technical Disclosure Bulletin, Oct. 1, 1996, US, pp. 157-160.*
International Search Report Application No. PCT/US 01/14908, mailed Jun. 27, 2002.
McMinn Brian D.
Miranda Paul C.
Advanced Micro Devices , Inc.
Kivlin B. Noäl
Lee Thomas
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Yanchus, III Paul
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