Static information storage and retrieval – Systems using particular element – Magnetic thin film
Reexamination Certificate
2003-06-16
2004-08-17
Elms, Richard (Department: 2824)
Static information storage and retrieval
Systems using particular element
Magnetic thin film
C365S158000, C365S171000, C365S230030, C365S230060
Reexamination Certificate
active
06778434
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to magnetic random access memory devices and particularly to those including memory cells having magnetic tunneling junctions (MTJs) (hereinafter also referred to as “MTJ memory cells”).
2. Description of the Background Art
A magnetic random access memory (MRAM) device includes as a memory device a device having a tunneling magneto-resistive (TMR) effect (hereinafter referred to as a “tunneling magneto-resistance element”). The tunneling magneto-resistance element has a magnetic tunnel junction structure and is formed of a first thin magnetic film providing a fixed direction of magnetization, a second thin magnetic film providing a direction of magnetization rewritable by a magnetic field externally applied, and a tunnel insulating film sandwiched between the first and second thin magnetic films.
A tunneling magneto-resistance element with the first and second thin magnetic films' magnetic moments parallel and anti-parallel in direction provides resistance having a minimum value Rmin and a maximum value Rmax, respectively. As such when the tunneling magneto-resistance element is used in an MTJ memory cell its magnetic moments' parallel and anti-parallel states are correlated to one and the other of storage data's logic levels “0” and “1”, respectively. The MTJ memory cell stores data, holding it in non-volatile manner until it is rewritten by a data writing magnetic field applied capable of inverting a direction of magnetization in the thin magnetic film that exceeds a threshold level.
Generally an MRAM device includes a digit line and a word line provided to correspond to a row of MTJ memory cells and corresponding to a write select line and a read select line, respectively, and a bit line corresponding to a data line provided to correspond to a column of MTJ memory cells to achieve random access. Thus MTJ memory cells are arranged to correspond to intersections of bit and digit lines.
In a data write a data write current is supplied to digit and bit lines, as addressed, selectively. Furthermore, designing so that a magnetic field acting on an MTJ memory cells when a data write current flows through both of corresponding digit and bit lines exceeds the aforementioned threshold level, allows digital data to be written to an MTJ memory cell having its address selected.
In a data read a word line is selected and responsively a selected MTJ memory cell's TMR device is electrically connected between a corresponding bit line and a source line, and the bit line and the source line are provided with a difference in potential to generate a current passing through the MTJ memory cell. The current is detected and data stored in the selected memory cell is read.
The MRAM device with the MTJ memory cell described above is noted as a rapidly, randomly accessible, non-volatile memory device. As compared with dynamic random access memory (DRAM), however, the MR device excessively requires a metal interconnection corresponding to the digit line described above.
In general, an MRAM device's chip fabrication cost is proportional to the number of process steps, and increased numbers of metal interconnection layers required contribute to increased chip fabrication cost. Furthermore in embedding an MRAM device together with a logic chip if the number of metal interconnection layers required for the logic portion is larger than that of metal interconnection layers required for an MTJ memory cell the use of the MRAM device as an embedded memory would provide increased fabrication cost.
Accordingly the number of interconnection layers in an MRAM device is reduced by providing a low ohmic connecting of a programming line corresponding to the aforementioned digit line and a word line together to eliminate a metal interconnection arranged to correspond to a column of memory cells, for example as disclosed in Japanese Patent Laying-Open No. 2002-175688.
The conventional configuration sharing digit and word lines, as disclosed in the publication, however, requires control so that in a data read the digit line do not have a current passing therethrough. This would require a transistor switch not only at one end of the digit line but opposite ends thereof. Furthermore in a data write as the digit line is supplied with a current the word line's potential also simultaneously increases and accordingly it is necessary to increase an access transistor's source potential to decrease a leak current in a non-selected memory cell. More specifically, a source line voltage control circuit is additionally required. As such, while the conventional configuration does provide a reduced number of interconnection layers, it requires an additional control circuit resulting in an increased circuit area.
When a memory device is increased in capacity, a configuration dividing a memory cell array into a plurality of subarrays to allow hierarchical address selection is adopted to reduce signal propagation delay. (Hereinafter this configuration will also be referred to as a “divided array configuration.”)
The divided array configuration, however, requires a hierarchical address select line. This results in a further increased number of metal interconnection layers required and hence increased chip fabrication cost. The divided array configuration may be provided with an address decoder arranged locally for each subarray. While this does avoid increased numbers of metal interconnection layers, the provision of multiple address decoders contributes to an increased chip area.
SUMMARY OF THE INVENTION
The present invention contemplates a magnetic random access memory device allowing a divided array configuration and the like to have reduced numbers of interconnection layers required for an address select line without increased chip areas.
The present invention provides a magnetic random access memory device comprised of: a memory cell array including a plurality of magnetic memory cells arranged in rows and columns, the memory cell array being divided into a plurality of subarrays arranged in rows and columns; and a plurality of global select lines provided to correspond to one of the rows and the columns of the plurality of magnetic memory cells commonly for the subarrays sharing one of the rows and the columns of the plurality of magnetic memory cells. The plurality of global select lines in each of data read and write operations is each set to a voltage corresponding to selection and non-selection of one corresponding thereto. The plurality of subarrays each include a plurality of bit lines provided to correspond to the plurality of magnetic columns, a plurality of select lines provided to correspond to one of the rows and the columns of the plurality of magnetic memory cells for selecting one of the rows and the columns of the plurality of magnetic memory cells in the subarray corresponding thereto, and a plurality of select line drivers provided to correspond to the plurality of select lines, respectively, to each drive a voltage of a corresponding one of the select lines in response to the voltage of a corresponding one of the global select lines. The plurality of magnetic memory cells each have a magneto-resistance element electrically connected to a corresponding one of the bit lines, and an access element electrically connected between the magneto-resistance element and one of the plurality of global select lines and the access element in the data read operation turns on or off in response to a result of a row select operation in a corresponding one of the subarrays, the access element in the data write operation is turned off regardless of the result.
A main advantage of the present invention is that in a magnetic random access memory device including a memory cell array divided into a plurality of subarrays to provide hierarchical address selection a consideration is provided not to impair address selection and in addition thereto a global select line can electrically be connected to an access el
Elms Richard
Le Toan
McDermott Will & Emery LLP
Renesas Technology Corp.
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