Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-09-26
2004-11-30
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S121000
Reexamination Certificate
active
06825694
ABSTRACT:
BACKGROUND
1. Field of the Present Invention
The present invention generally relates to the field of electronic circuits and more particularly to digital flip-flop circuits.
2. History of Related Art
Flip-flop circuits are well known in the field of digital electronics. Referring to
FIG. 1
, a typical flip-flop circuit
100
is depicted. Flip-flop circuit
100
is configured to receive a clock input (C) on a clock input node
122
and a data input (D) on a data input node
123
. Circuit
100
is further configured to produce a pair of complementary digital output signals comprising an output signal (Q) on an output node
126
and its logical complement output signal (QB) on output node
128
.
The operation of circuit
100
will be described with reference to
FIGS. 1 through 4
where
FIGS. 2
,
3
, and
4
are equivalent circuit representations of circuit
100
under various states and where “on” transistors are replaced with a source-to-drain short and “off” transistors are replaced with a source-to-drain open. As depicted in
FIG. 1
, circuit
100
includes n-channel transistors
101
through
106
, p-channel transistors
107
through
110
, and inverters
112
,
114
,
116
, and
118
. The p-channel transistors
107
through
109
are connected between Vdd and a control node
120
and their gate terminals are controlled by clock signal C, data signal D, and signal CBD respectively. The n-channel transistors
101
through
103
form a series connection between control node
120
and Vss or ground while their gate terminals are also controlled by signals C, D, and CBD respectively. The n-channel transistors
104
,
105
, and
106
form a series connection between output node
126
and Vss with their gates controlled by clock signal C, a control node
120
, and signal CBD respectively.
When clock signal C is low (steady state) as represented in
FIG. 2
, p-channel transistor
107
turns on and pulls control node
120
high. When clock signal C subsequently transitions from low to high (FIG.
3
), the state of control node
120
is determined by the state of input signal D for a duration or interval referred to herein as the clocking duration or clocking interval. The length of the clocking interval is determined by the series combination of inverters
112
through
116
. The low to high transition of signal C ripples through inverters
112
through
116
to produce on node
124
a high-to-low transition on a signal identified as CBD (C Bar Delayed), which is a time-delayed complement of clock signal C. When the transition of clock signal C ripples through to node
124
, CBD transitions low. When CBD is low (FIG.
4
), p-channel transistor turns on
109
and pulls control node
120
high. Thus, the series inverters
112
through
116
produce a clocking interval window during which C and CBD are both high following a low-to-high transition of clock signal C.
Returning to
FIG. 3
, which represents the state of circuit
100
during the clocking interval, if D is low, p-channel transistor
108
will turn on thereby maintaining control node
120
in its high state. If D is high, p-channel transistors
107
,
108
, and
109
are cut off and n-channel transistors
101
through
103
are turned on. In this state, control node
120
will be pulled low. Because, however, control node
120
is connected to the capacitive gate terminals of two transistors (
105
and
110
) and to the series resistance of transistors
101
through
103
, there will be an inherent delay associated with the high to low transition of control node
120
. Moreover, because control node
120
is connected to the gate electrode of the output transistor pair (transistor
105
and transistor
110
), any delay in the transition of control node
120
is propagated to output nodes
126
and
128
thereby negatively impacting performance. In addition, it will be apparent that the rise time and fall time associated with the depicted circuit configuration are unequal or asymmetrical because of the relatively long time it takes control node
120
to transition low. Asymmetrical timing in digital circuits is typically undesirable because timing requirements are typically understood to be independent of the data. It would be desirable, therefore, to implement a flip-flop circuit that achieved substantially symmetrical performance at low power and without a significant increase over the cost, complexity, and size of the circuit
100
.
SUMMARY OF THE INVENTION
The problems identified above are in large part addressed by a flip-flop circuit according to the present invention in which a clock signal and a data input signal are received and a corresponding output produced. The circuit includes a set of series inverters connected to the clock signal to produce a delayed and complementary copy of the clock signal. The circuit further includes a set of three p-channel connectors connected in parallel between a supply voltage (Vdd) and a control node. The p-channel transistor gates are driven by the clock signal, the data signal, and the delayed signal. The circuit further includes three n-channel transistors connected in series between the control node and Vss and gated by clock signal C, data signal D, and the delayed signal. The control node controls the gate of a fourth p-channel transistor connected between Vdd and an output node. A set of three n-channel transistors is connected between the output node and ground. The gates of these transistors are controlled by the clock signal, the delayed signal, and an inverted copy of the data signal, which is provided directly to one of these output transistors via a control inverter. In one embodiment, the n-channel transistor string between the control node and ground and the n-channel transistor string between the output node and ground may share a common transistor having a W/L roughly twice that of the other n-channel devices. The output node may be connected to a stabilization circuit to improve noise immunity.
REFERENCES:
patent: 5796282 (1998-08-01), Sprague et al.
patent: 6496038 (2002-12-01), Sprague et al.
Chang Daniel D.
International Business Machines - Corporation
Lally Joseph P.
Salys Casimer K.
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