Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-04-05
2004-10-12
Kim, Hong (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S105000, C711S005000, C365S230030, C365S230040, C365S233100, C713S400000, C713S401000
Reexamination Certificate
active
06804756
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a synchronization circuit for read paths of an electronic memory, particularly a non-volatile memory, organized into two separate memory banks.
DESCRIPTION OF THE RELATED ART
It is known that conventional non-volatile memories have, in their fundamental structure, a single memory matrix which can be addressed and read.
The memory read processes are performed one after the other in a mutually exclusive manner, i.e., never simultaneously.
Two successive read cycles in fact could not be activated simultaneously, since their temporal overlap would entail the mutual destruction of the paths (which would compete with each other) and of the data (which would tend to conflict).
This is evident, and accordingly conventional non-volatile memories are managed so as to produce a single read signal stream at a time.
Although this procedure is simple and reliable, it is slow for certain applications which require high performance in terms of memory read speed.
The read performance of the conventional approach is in fact evidently limited not only by factors linked to the technology, but also by the need to disallow read speeds higher than the fastest complete propagation of all the signals of the read stream of a memory read cycle.
SUMMARY OF THE INVENTION
The present invention solves the drawbacks of the aforementioned techniques by organizing non-volatile memories into two separate banks to develop a so-called interleave read mode.
This mode, which is the subject of co-pending patent applications in the name of this same Applicant, is carried out by starting two separate and mutually independent read processes and keeping them active.
In general, the timing stimulus for starting the two read processes occurs, under the supervision of an external control signal (RD), at separate times which are mutually spaced in the so-called burst mode. The two main intervals of a read cycle, i.e., the pre-charging step and the step for evaluating the data item to be read, can be performed without necessarily being mutually exclusive as regards the evaluation step.
However, in order to avoid malfunctions due to noise, it is necessary to provide synchronization of the read steps, so as to perform the evaluation in an exclusive manner on just one of the two memory banks. It is also necessary to synchronize the connection between the sense amplifier and the output buffer, subjecting it to the control of the memory bank that has been evaluated and making its communication dependent on the protocol conditions.
The present invention is to provide a synchronization circuit for read paths of an electronic memory which allows to synchronize the read streams so as to allow the evaluation step exclusively on one of the two banks into which an electronic memory is divided, although having two simultaneous read streams.
REFERENCES:
patent: 5291580 (1994-03-01), Bowden, III et al.
patent: 5526311 (1996-06-01), Kreifels et al.
patent: 5559990 (1996-09-01), Cheng et al.
patent: 5696917 (1997-12-01), Mills et al.
EPO: European Search Report EP 00 83 0269, Aug. 9, 2000.
Jenkens & Gilchrist P.C.
Kim Hong
STMicroelectronics S.r.l.
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