Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-12-11
2004-08-17
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S023000
Reexamination Certificate
active
06779170
ABSTRACT:
The present invention relates to a novel method and apparatus for performing logic emulation. More specifically, the present invention provides logic emulation by using waferscale integration.
BACKGROUND OF THE DISCLOSURE
Logic emulation has become an important aspect of ASIC verification. Logic emulation allows users to create a hardware model of a chip design by using emulation software that maps the design onto reprogrammable circuitry or emulation systems. Specifically, emulation systems often use arrays of discrete programmable logic devices (PLDs), e.g., hundreds of logic processors, such as Field Programmable Gate Arrays (FPGAs), which can mimic the operation of an ASIC design prior to fabrication. This “virtual silicon” is a functional equivalent of the actual chip, operating at close to real time, thereby assuring correct timing relationships.
For example,
FIG. 1
illustrates a conventional emulation system having a plurality of printed circuit boards (PCBs) that are in communication with each other with each board containing a plurality of FPGAs. When a chip design or design under test (DUT) is emulated using such a system, the DUT is often expressed as a netlist. The netlist represents the interconnection of circuit elements and the descriptions of the connections among those circuit elements. In other words, the netlist describes a list of elements such as gates, rams, flip-flops, and the wires that go between these elements. In operation, the netlist is mapped onto the FPGAs of the emulation system by using mapping software typically provided by the vendor of the emulation system. The mapping process typically requires a partitioning step where the netlist is partitioned into portions or partitions, where each partition is mapped onto a FPGA. In turn, each FPGA is then complied to map the logical functionality encapsulated by that partition onto the programmable resources of that FPGA. Additionally, the designer would have to ensure that the interconnect resources available on each PCB are compatible with that particular partition.
Thus, logic emulation has transformed electronic design by enabling early integration and hardware-software coverification. Namely, logic emulation allows designers to test their designs before committing to the costly action of fabricating chip prototypes.
However, as chip designs continually increase in complexity, designers are facing various logic emulation pitfalls. First, as chip designs get larger and more complex, the cost and size of the logic emulation system must also increase accordingly. Specifically, referring to
FIG. 1
, as the size and complexity of the DUT is increased, the emulation system allows for expansion by connecting additional PCBs to the system. Unfortunately, the connections between the PCBs and the connections between the FPGAs are themselves limiting factors, because these interconnections are physically limited. These physical limitations at the boundaries of the FPGAs and at the boundaries of the PCBs create tremendous pressure on the partitioning software to properly identify a partitioning point in the DUT to cut the design so that the limited number of connections available is enough to accommodate a particular partition. In sum, traditional emulation systems have limited routability and mapability due to physical constraints.
Second, conventional emulation systems limited by their interconnect and internal architecture of the PLDs will force a designer to implement “time slice” operations, where multiple cycles of time in the emulation system are required to use the limited interconnections to transfer one equivalent clock worth of data as designed in the DUT. For example, if there are a thousand interconnections between two PCBs and the DUT dictates a transfer of three thousand signals for a given clock cycle, then it is necessary in practice to take three clocks to accomplish the transfer. The use of the time slice approach adds another layer of complexity in the emulation process because the software must now track the completion of multiple transfers before a signal can be declared. Thus, as the complexity of the DUT increases, the size and cost of the emulation system also increase rapidly while performance drops.
Additionally, the level of confidence that the emulation system is performing its functions is also jeopardized. Namely, the emulation software is severely pressured to address complicated demands arising from limited interconnections and the use of multiple time slices to transfer data. Commonly, debugging operations often uncover software bugs directly caused by the FPGA complier or the partitioning software. Namely, the emulation tool itself creates errors that must be addressed by the designer.
Therefore, a need exists for a novel method and apparatus that is capable of providing logic emulation to address increasing complexity of chip designs while providing a lower cost structure, a smaller system size, and natural flexibility in defining and distributing logic and routing functions.
SUMMARY OF THE INVENTION
In one embodiment of the present invention, a novel method and apparatus for providing logic emulation is disclosed. Specifically, the present invention provides logic emulation by using waferscale integration.
The present invention uses a semiconductor wafer to build a sea of soft-programmable logic cells and interconnections. One unique aspect of the present invention is that the cells are homogeneous to such an extent that even flip-flops are constructed from these programmable logic cells. In other words, the fine granularity of the programmable logic cells provides routability and mapability that are not achievable by traditional emulation systems.
The cells implemented on the wafer include, but are not limited to input/output transceiver cells, function or logic cells, routing cells, and clock generating cells. The input/output transceiver cells provide the physical attachments for receiving and sending signals to and from an external device, e.g., a target board.
The function or logic cells are programmable such that the output of the logic cell is an arbitrary function of the inputs. For example, a three-bit input (a, b, c) logic cell will produce an output y(a,b,c). In one embodiment, the three-bit input logic cell will have an eight-bit storage set of values that amount to a truth table.
The routing cells are selectable so that one of its inputs is passed or routed to its output. In one embodiment, the routing cell is implemented as an 8-to-1 routing cell.
Finally, the clock generating cells produce clock signals for other cells on the wafer. In one embodiment, two different clock signals of differing phases are generated from a single waveform, e.g., a square waveform.
In operation, a netlist for a DUT is mapped onto the cells of the wafer, i.e., mapping software is used to map a candidate design onto the programmable resources on the wafer. Since wafers usually have some defective regions, software tools are used to identify those regions so that the design mapping software will avoid mapping portions of the netlist onto the defective regions.
Compared to the traditional PLD systems, the present wafer-scale emulation system has several advantages such as lower cost, smaller size, and higher ratio of interconnect (wiring) to logic elements. Programmable elements can be targeted to the logic emulation function, and as a result non-logic-gate functions like RAMs and clock distribution can be implemented with more efficiency and greater flexibility. The logic and routing functions can be defined in tandem with the software which maps a design to those functions, whereas a conventional system must adapt partitioning and routing software to the limited interconnect and internal architecture of PLDs. Finally, software quality and reliability (e.g., number of bugs) for the present wafer-scale system should be better when compared to a traditional emulation system, because the present software is not pressured to address the constraints of FPGA and PCB boundaries.
REFE
Garbowski Leigh M.
Moser Patterson & Sheridan LLP
NVIDIA Corporation
Rossoshek Helen
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