Dual threshold buffer with hysteresis

Details Dual threshold buffer with hysteresis Dual threshold buffer with hysteresis

2003-02-24

2004-08-10

Wamsley, Patrick (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C327S074000, C327S206000

Reexamination Certificate

active

06774676

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to buffers, and more particularly to buffers having dual thresholds.
BACKGROUND OF THE INVENTION
Signal transmission busses may use discrete voltage levels to convey digital information. Many transmission busses convey digital information using “high” and “low” voltage levels. The high and low voltage levels can be any useful voltage levels and are not necessarily centered about a mid-supply voltage. Oftentimes, analog or mixed signal integrated circuits use relatively higher voltage supply levels, which may require detecting threshold values that are not centered about a mid-supply voltage. For example, GTL logic threshold levels are typically 0.4V for a “low” logical input, and 0.8V for a “high” logical input. In circuits where the voltage supply level (e.g. Vcc) is 3.3V for an integrated circuit, the GTL logic threshold levels are not centered about the mid supply voltage (i.e., 1.65V).
SUMMARY OF THE INVENTION
The present invention is directed to a buffer having dual thresholds. According to one aspect of the invention, a buffer having an input terminal and an output terminal comprises a current source, first through fourth transistors, a current mirror, and an output driver. The first current source is configured to produce an overall current. The first transistor is configured to produce a first current in response to a first threshold voltage. The second transistor is configured to produce a second current in response to a second threshold voltage when the output of the buffer is equivalent to a first logic state. The third transistor is configured to produce a third current in response to a voltage at the input terminal. The fourth transistor is configured to produce a fourth current in response to the voltage at the input terminal when the output of the buffer is equivalent to the first logic state. The current mirror is configured to receive the first and second currents to produce a first grouped current at a first node, receive the third and fourth currents to produce a second grouped current at a second node, and reflect a selected one of the first and second grouped currents to produce a reflected current at a selected one of the first and second nodes, such that a voltage is produced at the selected node in response to the reflected current and the grouped current that is not reflected. The output driver is configured to produce an output voltage at the output terminal in response to the voltage produced at the selected node.
According to another aspect of the invention, a method for providing buffering with hysteresis for an input signal comprises producing a first current in response to a first threshold voltage. The second current is produced in response to a second threshold voltage when the output of the buffer is equivalent to a first logic state. A third current is produced in response to a voltage at the input terminal. The fourth current is produced in response to the voltage at the input terminal when the output of the buffer is equivalent to the first logic state. The first and second currents are received at a first node such that a first grouped current is produced. The third and fourth currents are applied to a second node such that a second grouped current is produced. A selected one of the first and second grouped currents is mirrored to produce a reflected current at a selected one of the first and second nodes whereby a voltage is produced in response to the reflected current and the grouped current that is not reflected. An output voltage is produced for the buffer in response to the voltage produced at the selected node.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of illustrated embodiments of the invention, and to the appended claims.


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patent: 5256916 (1993-10-01), Thurston
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patent: 6023174 (2000-02-01), Kirsch
patent: 6084433 (2000-07-01), Momtaz
R. Jacob Baker et al., “CMOS Circuit Design, Layout, and Simulation”,IEEE Press Series on Microelectronic Systems, p. 357, 1998.

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