Semiconductor device having an MIS transistor

Details Semiconductor device having an MIS transistor Semiconductor device having an MIS transistor

2003-01-13

2004-08-10

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S377000, C257S382000

Reexamination Certificate

active

06774441

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having an MIS (Metal-Insulator Semiconductor) transistor, and more particularly, to a semiconductor device having an MIS transistor in which a metal silicide layer is formed on source and drain regions through application of a salicide process.
2. Description of the Background Art
In recent years, a salicide process is often used in manufacturing of a semiconductor device in order to increase the operating speed of the semiconductor device. The salicide process is to form a metal silicide layer in self alignment simultaneously on a gate electrode and on source and drain regions formed on a silicon substrate which is a semiconductor substrate. By employing such a process, the resistance in the source and drain regions can be lowered, while the operating speed of the MIS transistor can be increased.
In order to meet the recent demand of size reduction in semiconductor devices, a self align contact structure is coming to be essential. The self align contact structure is to form a sidewall insulating film or the like at an upper part or a side surface of the gate electrode, using a film having a high etching selectivity to an interlayer insulating film covering the gate electrode, to form a contact for a gate electrode in self alignment. The self align contact structure allows a microscopic contact to be formed with a good yield, enabling miniaturization of semiconductor devices.
In a semiconductor device in which the self align contact structure is employed, an insulating film comprised of two layers of a silicon oxide film and a silicon nitride film is often used as a sidewall insulating film. Here, the silicon nitride film is for ensuring a high etching selective ratio to the silicon oxide film of an interlayer insulating film at opening of a contact hole. The silicon oxide film serves as an underlay for relieving intrinsic stress occurring when the silicon nitride film is deposited directly on the gate electrode or silicon substrate. Moreover, the silicon oxide film is less likely to capture hot carriers compared to the silicon nitride film, so that it may be interposed between the silicon nitride film and the silicon substrate surface to improve the electrical characteristics and reliability of the MIS transistor. It is noted that reduction of the width of the sidewall insulating film is increasingly required so as to conform to miniaturization of semiconductor devices.
In general, the silicon substrate also includes thereon an MIS transistor in which no metal silicide layer is formed. An example thereof is an MIS transistor used for an input/output circuit, which has no metal silicide layer formed on the source and drain regions so as to ensure the gate oxide film resistance and the ESD (Electrostatic Discharge) resistance. Thus, both a circuit region in which a metal silicide layer is formed and a circuit region in which no metal silicide layer is formed are present on the same semiconductor substrate.
FIGS. 12
to
16
show process steps of a method of manufacturing a conventional semiconductor device that has the self align contact structure described above and that employs the salicide process.
FIG. 17
is a section view showing the structure of the conventional semiconductor device manufactured by the method. It is noted that the section shown in the drawings is of the circuit region in which a metal silicide layer is formed, and the circuit region in which no metal silicide layer is formed is not shown.
First, as shown in
FIG. 12
, a silicon oxide film
2
a
which is to be a gate insulating film of the MIS transistor is deposited, and a polysilicon film is further deposited thereon, which is patterned by a photolithography technique, to form a gate electrode
3
. Next, ions are implanted into a main surface of silicon substrate
1
at positions where gate electrode
3
is arranged in between, to form LDD (Lightly Doped Drain) regions
4
a
,
5
a
that are n
−
-type diffusion regions having relatively shallow junction depths. LDD regions
4
a
,
5
a
are diffusion regions that are to be a part of source and drain regions.
Subsequently, as shown in
FIG. 13
, silicon oxide film
6
a
and silicon nitride film
7
a
are sequentially deposited on the entire main surface of silicon substrate
1
so as to cover gate electrode
3
. Here, silicon oxide film
6
a
serves as an underlay of silicon nitride film
7
a.
Subsequently, silicon nitride film
7
a
and silicon oxide film
6
a
are etched back by anisotropic etching, to form a sidewall insulating film
8
at a side surface of gate electrode
3
, as shown in FIG.
14
. Here, sidewall insulating film
8
is comprised of two layers of an oxide sidewall film
6
having an L-shaped section and a nitride sidewall film
7
arranged thereon. Further, the side surface of gate electrode
3
and the main surface of silicon substrate
1
are both covered with oxide sidewall film
6
.
Next, as shown in
FIG. 14
, ions are implanted into the main surface of silicon substrate
1
, using sidewall insulating film
8
and gate electrode
3
as a mask, to form heavily-doped source region
4
b
and heavily-doped drain region
5
b
that are n
+
-type diffusion regions to be a part of the source and drain regions. It is noted that heavily-doped source region
4
b
and heavily-doped drain region
5
b
are diffusion regions having junction depths greater than those of LDD regions
4
a
,
5
a.
Before forming a metal silicide layer on source and drain regions
4
,
5
, an insulating film, which is to be a silicide-formation preventing film for preventing silicidation of the MIS transistor arranged in a circuit region in which no metal silicide layer is to be formed, is deposited on the entire main surface of silicon substrate
1
. Thus, as shown in
FIG. 15
, the MIS transistor in which a metal silicide layer is to be formed is also covered with silicide-formation preventing film
9
. A silicon oxide film is generally used for silicide-formation preventing film
9
deposited here, having a certain degree of thickness (e.g. at least 50 nm) in order to prevent a reaction in the circuit region in which no metal silicide layer is to be formed.
Next, as shown in
FIG. 16
, silicide-formation preventing film
9
on the MIS transistor in which a metal silicide layer is to be formed is removed. Here, sufficient etching is performed so as to completely remove silicide-formation preventing film
9
in the circuit region in which a metal silicide layer is to be formed. This is because residue of silicide-formation preventing film
9
due to insufficient etching would hinder formation of a metal silicide layer.
In the etching process of silicide-formation preventing film
9
, a film thickness of silicide-formation preventing film
9
is relatively thick, increasing the amount of over etching for the film thickness, resulting in a large amount of etching in total. Thus, wet etching or the combination of dry and wet etching is used to remove silicide-formation preventing film
9
, since dry etching alone would have higher possibility of causing a damage on the MIS transistor. This partially removes a lower end of oxide sidewall film
6
having an L-shaped section which is a part of sidewall insulating film
8
, producing a removed-portion
6
d
as shown in FIG.
16
.
Next, to form a metal silicide layer, a cobalt (Co) layer is deposited over the entire main surface of silicon substrate
1
, which is then subjected to thermal treatment. This allows an Si atom to react with a Co atom at the interface between silicon substrate
1
and the cobalt layer, which forms cobalt suicide layers
10
,
11
consisting of CoSi
2
simultaneously on gate electrode
3
and on source and drain regions
4
,
5
.
Subsequently, an unreacted cobalt layer is removed to form an MIS transistor having a reduced size by the self-align contact structure and an increased operating speed by a so-called salicide structure.
The semiconductor device manufactured by the co

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