High speed address sequencer

Details High speed address sequencer High speed address sequencer

2001-07-30

2004-03-02

Verbrugge, Kevin (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S219000

Reexamination Certificate

active

06701423

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to address sequencers, and more particularly, to a high speed address sequencer for generating addresses to access a memory device.
BACKGROUND OF THE INVENTION
Memory circuits, such as FLASH memory, require address generation or sequencer circuits to generate address values for various memory functions. For example, during burst mode operation of a flash memory, an address sequencer generates sequential addresses in response to a clock signal. Since memory densities have become higher and memory speeds faster, it has become necessary to have faster address sequencers.
FIG. 1
shows a portion of a typical address sequencer
100
that provides address generation for use with a memory device. The sequencer
100
includes address stages
102
,
104
and
106
that are coupled together to allow address toggle signals (Tgl) to propagate from one stage to the next stage. A clock signal (CLK) and an inverted version of the clock signal (CLK*) are provided to the address stages to provide timing for address generation and the propagation of the Tgl signals. During operation, sequential address signals (Ad) are generated by the address stages and used to access the memory device.
FIG. 2
shows a detailed view of the address stage
106
. During operation of the address stage
106
, an address signal Ad
n
* is received and used to set an initial value of A
n
. As shown in a detailed circuit
108
, during the initialization, an address load signal (Aload) goes to a high state so that the signal Ad
n
* can propagate to the node “a”. This occurs while the CLK signal stays at a low state.
When the CLK signal goes to a high state, the address stage output changes states dependant upon the state of the Tgl
(n−1)
signal. If the signal A
n
is in a high state and the toggle signal Tgl
(n−1)
is in a high state, then the signal Tgl
(n)
will be in a high state, which makes the signal A
n+1
of the next stage change states. Since the Tgl signals are connected in series (i.e. stage to stage) and have to change states within one CLK cycle, the propagation time of the Tgl signals through all the address stages may limit what the maximum CLK cycle speed can be.
FIG. 3
shows a timing diagram
300
that illustrates the signal timing of signals associated with the address stage
106
of FIG.
2
. If Tgl
(n−1)
goes to the high state at cycle T
−1
, the signal A
n
will go to the high state at cycle T(o). Furthermore, A
n
will not change its state until clock cycle T
2
n
. As a result, the typical address sequencer limits the usable clock speed, since all stages must toggle within one clock cycle, and as a result, the propagation delay associated with the toggle signals begins to limit the usable clock speed.
Therefore, it would be desirable to have an address sequencer that overcomes the clock speed limitations present in current address sequencers.
SUMMARY OF THE INVENTION
The present invention includes an address sequencer system that overcomes limitations on usable clock speeds present in typical address sequencers. The sequencer design includes the generation of a secondary clock signal that is used to clock selected stages of the address sequencer. The cycle time of the secondary clock is longer than that of a main clock. Thus, the stages of the address sequencer driven by the secondary clock have a longer time to propagate address state changes.
In one embodiment of the invention, an address sequencer circuit for generating sequential addresses for accessing a memory device is provided. The address sequencer includes a plurality of address stages that are coupled together, and also includes a first clock generation circuit that receives an input clock and generates a first clock signal that is coupled to a first portion of the address stages. A second clock generation circuit is provided that receives the input clock and a toggle signal and generates a second clock signal that is coupled to a second portion of the address stages.
In anther embodiment of the invention, a method for generating sequential addresses from an address sequencer is provided. The address sequencer is used to access a memory device and the address sequencer includes a plurality of address stages that are coupled together. The method includes steps of receiving an input clock signal, generating a first clock signal from the input clock signal, wherein the first clock is coupled to a first portion of the address stages, and generating a second clock signal from the input clock signal and a toggle signal, wherein the second clock signal is coupled to a second portion of the address stages.


REFERENCES:
patent: 6038648 (2000-03-01), Nakaoka
patent: 6209076 (2001-03-01), Blomgren

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