Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-11-14
2004-11-23
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S391000, C257S394000, C257S396000
Reexamination Certificate
active
06822300
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a memory cell structure of a semiconductor memory device such as a loadless-type CMOS static memory (hereinafter referred to as “SRAM (Static Random Access Memory)”) or a loadless-type associative memory (CAM: Content Addressable Memory).
2. Description of the Background Art
FIG. 31
is a view showing the conventional layout configuration of a loadless-type SRAM memory cell formed of four transistors. An equivalent circuit diagram thereof is shown in FIG.
19
.
This type of SRAM is shown in, for example, “A 1.9-um
2
Loadless CMOS Four-Transistor SRAM Cell In a 0.18-um Logic Technology,” in the international academic journal IEDM, pp. 643-646, 1998 or in “An Ultrahigh-Density High-Speed Loadless Four-Transistor SRAM Macro with Twisted Bitline Architecture and Triple-Well Shield,” in the international thesis journal IEEE JSSC, VOL. 36, No. 3, March 2001.
As shown in
FIG. 31
, a memory cell
1
has four MOS (metal oxide semiconductor) transistors. Concretely, memory cell
1
has NMOS transistors N
1
, N
2
formed in a P well and PMOS transistors P
1
, P
2
formed in an N well.
NMOS transistor N
1
is formed in an intersection portion between an N-type diffusion region
2
a
and a polysilicon interconnection
3
c
while NMOS transistor N
2
is formed in an intersection portion between an N-type diffusion region
2
b
and a polysilicon interconnection
3
b.
PMOS transistor P
1
is formed in an intersection portion between a P-type diffusion region
2
c
and a polysilicon interconnection
3
a
while PMOS transistor P
2
is formed in an intersection portion between a P-type diffusion region
2
d
and a polysilicon interconnection
3
a.
PMOS transistors P
1
and P
2
are access transistors while NMOS transistors N
1
and N
2
are driver transistors. Diffusion regions
2
a
to
2
d,
respectively, are connected to upper layer wires via contact holes
4
a
to
4
h.
In the layout configuration shown in
FIG. 31
, a word line WL is arranged in the lateral direction. Contrarily, a pair of bit lines BL
1
and BL
2
is arranged in the longitudinal direction. As shown in
FIG. 23
, the layout configuration of one bit is long in the longitudinal direction and bit lines become long according to such a layout configuration.
As described above, the SRAM memory cell of a four transistor configuration according to the prior art becomes long in the bit line direction and, therefore, the wire capacitance of the bit lines becomes large. In addition, the interval between bit lines BL
1
and BL
2
becomes narrow so that the capacitance between the bit lines also becomes large. Therefore, there is a problem that the access time is slow.
Furthermore, the direction of the gates and diffusion regions of access transistors P
1
and P
2
and the direction of the gates and diffusion regions of driver transistors N
1
and N
2
differ so that the dispersion of the width of the patterns or of the pattern formation positions for forming the gates, and the like, becomes large after photolithographic processing. Therefore, the dispersion of the width or of the formation positions of the gates, and the like, becomes great.
In the case that the dispersion of the gate width, and the like, becomes great, the characteristics of each of the above described transistors fluctuate. In addition, in the case that the formation position of, for example, polysilicon interconnection
3
c
shifts in the left to right direction in
FIG. 23
, polysilicon interconnection
3
c
and contact hole
4
a
or
4
b
are short circuited while in the case that the formation position of polysilicon interconnection
3
a
shifts in the upward to downward direction in
FIG. 23
, polysilicon interconnection
3
a
and contact hole
4
e
to
4
g
are short circuited. When a gate pattern shifts in any direction, upward, downward, to the left or to the right, there is a possibility that the gate pattern forms a short circuit with a contact hole that is supposed to be isolated and, therefore, there is a problem that it is difficult to secure a margin against dispersion occurring during manufacture due to a mask shift, or the like.
Above described problems may occur not only in a memory cell of a loadless four-transistors type SRAM but also in a memory cell of a loadless four-transistors type CAM.
SUMMARY OF THE INVENTION
The present invention is made to solve the above described problems. An object of the present invention is to reduce the wire capacitance of bit lines and the capacitance between bit lines and to secure a margin concerning dispersion in manufacture of a semiconductor memory device such as an SRAM or a CAM.
A semiconductor memory device according to one aspect of the present invention includes: second and third wells of a second conductive type, formed on both sides of a first well of a first conductive type; first and second access MOS transistors of the first conductive type, formed on said second or third well; first and second driver MOS transistors of the second conductive type, formed on said first well; a word line connected to the gates of the first and second access MOS transistors, and extending in the direction along which the first, second and third wells are aligned; and first and second bit lines connected to the sources of the first and second access MOS transistors, respectively, and extending in the direction perpendicular to the direction along which the first, second and third wells are aligned. Then, first and second diffusion regions of the first conductive type for forming the sources/drains of the first and second access MOS transistors and third and fourth diffusion regions of the second conductive type for forming the sources/drains of the first and second driver MOS transistors extend in the same direction, and the gates of the first and second access MOS transistors and the gates of the first and second driver MOS transistors extend in the same direction.
As described above, the first and second bit lines extend in the direction perpendicular to the direction along which the first to third wells are aligned and, thereby, the first and the second bit lines can be made short and the spaces between the bit lines can be made wide. Furthermore, the above described first, second, third and fourth diffusion regions extend in the same direction while the gates of the access MOS transistors and the gates of the driver MOS transistors extend in the same direction and, thereby, the dispersion in the width of the patterns and in the formation positions of the patterns for forming the gates, and the like, can be kept small after photolithographic processing. In addition, in the case that the gates shift in the direction of their extension (longitudinal direction), short circuiting can be avoided between the gates and contact holes that are provided on both sides of the gates in the width direction of the gates.
It is preferable to arrange the first and second access MOS transistors, respectively, on the above described second and third wells. Thereby, the space between the first and second bit lines can be secured widely.
It is preferable to further provide a conductive part for directly connecting the drain of the first access MOS transistor and the drain of the first driver MOS transistor. Example of this conductive part includes a metal wire for directly connecting between contact parts formed on the above described drains or the integration (shared contact) of these contact parts formed of a conductive part filled in into the space over and between the drains.
By providing such a conductive part, the drains can be connected without the intervention of the gates of the driver MOS transistors so that the resistance of the connection between the drains can be reduced.
It is preferable for the gates of the above described first and second access MOS transistors and gates of the first and second driver MOS transistors to extend along a line in the direction perpendicular to the
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