Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-12
2004-11-30
Blum, David S. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S408000
Reexamination Certificate
active
06825528
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a source/drain region having a reduced area and a reduced parasitic capacitance and parasitic resistance. The present invention also relates to a method for producing the same, and an information processing apparatus.
BACKGROUND ART
Recently, the integration level of a semiconductor device is becoming higher and higher. There is an increasing demand for even smaller elements. In the case of a typical insulated gate type field effect transistor, as the size thereof is made smaller, the following problems become more significant: variations in threshold voltage due to variations in gate length caused upon manufacturing; an increase in off-leakage current due to degradation of sub-threshold characteristics; degradation of transistor characteristics due to a short channel effect such as punch-through.
There are known methods for solving the above-described problems which become evident due to size reduction. In one of the known methods, the junction of the source/drain region adjacent to the channel region of a transistor is formed at a shallow level. The term “source/drain region” means a source or drain region, or source and drain regions. To form the shallow junction, the source/drain regions are provided on opposite sides of a gate electrode via a gate electrode side wall insulating film, and are each accumulated to a level higher than a channel region (i.e., a surface of a semiconductor substrate under the gate electrode where the surface will be reversed by electric field of the gate electrode). Such source/drain regions are referred to as accumulated diffusion layer.
FIGS.
43
(
a
) to (
c
) are diagrams showing the steps of producing a conventional accumulated diffusion layer. Hereinafter, the steps of producing a conventional accumulated diffusion layer will be described with reference to FIGS.
43
(
a
) to (
c
).
As shown in FIG.
43
(
a
), a surface of a semiconductor wafer
1001
includes an isolation region
1002
and an active region
1003
. A silicon oxide film
1042
is provided in the isolation region
1002
. In the active region
1003
, the silicon substrate
1001
(semiconductor wafer) is exposed.
In the production steps of a conventional accumulated diffusion layer, initially, a gate electrode
1005
is formed on the active region
1003
via a gate insulating film
1004
. The top and the side walls of the gate electrode
1005
are covered with an insulating film
1006
.
Thereafter, as shown in FIG.
43
(
b
), a silicon film
1007
is grown by a selective epitaxial growth method only on an exposed region (active region
1003
) of the silicon substrate
1001
. The silicon film
1007
will become a semiconductor accumulated diffusion layer and serve as a source/drain region. The selective epitaxial growth method is disclosed in Japanese Laid-open Publication No. 61-196577, for example.
Thereafter, as shown in FIG.
43
(
c
), an interlayer insulating film
1008
is provided. A conductor
1010
formed on the interlayer insulating film
1008
is connected to the silicon film
1007
(source/drain region) via a contact conductor
1009
. The silicon film
1007
is made of epitaxial silicon, polycrystalline silicon, or the like.
In the conventional technique described with reference to FIGS.
43
(
a
) to (
c
), after the silicon film
1007
has been provided to a level higher than the channel region, impurity ions are implanted into the silicon film
1007
in the vicinity of the channel region to form a source/drain region.
The impurity ions are implanted into the silicon film
1007
which has been accumulated to a level higher than the channel region, so that the junction depth of the impurity diffused layer of the source/drain region can be made shallow. Thereby, the short channel effect can be effectively prevented.
As shown in FIG.
43
(
c
), a contact hole for the contact conductor
1009
is provided in the silicon film
1007
(source/drain region) which is positioned between the gate electrode
1005
and the isolation region
1002
. A length Ld along the gate length direction (perpendicular to the longitudinal direction of the gate electrode) of the source/drain regions
1007
cannot be less than (an alignment margin between the gate electrode and the contact)+(a width along the gate length direction of the contact hole)+(an alignment margin between the contact and the source/drain region).
Therefore, there is a problem with the semiconductor device of FIG.
43
(
c
) in that it is difficult to reduce the planer size of the source/drain region.
Japanese Laid-open publication No. 10-335660 discloses a method which provides a solution to the above-described problem.
FIG. 44
is a diagram showing an insulating gate type field effect transistor disclosed in Japanese Laid-open publication No. 10-335660.
In the insulating gate type field effect transistor, isolation insulating regions
2002
are disposed below a gate electrode
2005
in a semiconductor substrate
2001
. A region between the isolation insulating regions
2002
is called a device region. A distance between a side of the gate electrode
2005
and a point of one of the isolation insulating regions
2002
contacting a portion of the device region in which two diffusion layers
2012
and
2013
are provided is less than or equal to the height of the gate electrode
2005
. A distance between an edge at the gate electrode side and an edge at the isolation insulating region side of the upper diffusion layer
2012
is greater than or equal to the height of the gate electrode
2005
. The edge at the isolation insulating region side of the upper diffusion layer
2012
is disposed on the isolation insulating region
2002
.
FIGS.
45
(
a
) to (
e
) are diagrams showing a production process of the insulating gate type field effect transistor disclosed in Japanese Laid-open publication No. 10-335660.
FIG.
45
(
a
) shows a structure resulting from the following steps in the production process of the insulating gate type field effect transistor provided in a semiconductor device. An isolation insulating region
3002
is formed in a first conductivity semiconductor substrate
3001
, providing a device region surrounded by the region
3002
. In this case, a distance between a side of a gate electrode
3005
which will be provided in the device region and a point of the isolation insulating region
3002
contacting a portion of the device region in which two diffusion layers will be provided is less than or equal to the height of the gate electrode
3005
. A well region
3014
is formed in the device region. A gate insulating film
3003
is formed on the device region. The gate electrode
3005
is formed on the gate insulating film
3003
. Second conductivity impurities are implanted into the device region by an ion implantation method using the gate electrode
3005
as a mask, the second conductivity being different from the first conductivity. Thereby, a shallow diffusion layer
3013
(lower diffusion layer) is provided in the vicinity of a surface of the device region.
FIG.
45
(
b
) shows a structure resulting from the following steps. An oxide film is deposited on the gate insulating film
3003
by a chemical vapor growth method. Unwanted portions of the oxide film and the gate insulating film
3003
are removed by anisotropic etching. An insulating gate side wall
3007
is formed at a side of the gate electrode
3005
in a self alignment way.
FIG.
45
(
a
) shows a structure resulting from the following steps. A polycrystalline silicon film
3015
is deposited to the same height as that of the gate electrode
3005
.
FIG.
45
(
d
) shows a structure resulting from the following steps. An upper diffusion layer
3012
is provided. In this case, a distance between an edge at the gate electrode side and an edge at the isolation insulating region side of the upper diffusion layer
3012
is greater than or equal to the height of the gate electrode
3005
. The edge at the isolation insu
Adachi Kouichiro
Iwata Hiroshi
Kakimoto Seizo
Nakano Masayuki
Shibata Akihide
Birch Stewart Kolasch & Birch, LLP.
Blum David S.
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