Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-04
2004-02-10
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S347000, C257S369000
Reexamination Certificate
active
06690075
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device that uses a semiconductor film having crystallinity and a manufacturing method of such a semiconductor device. In particular, the invention relates to a semiconductor device having a CMOS structure that uses a silicon film as a semiconductor film.
2. Description of the Related Art
In recent years, the CMOS technology using insulated-gate transistors has been developed extensively. However, as described in Japanese Unexamined Patent Publication Nos. Hei. 4206971 and Hei. 4-286339, transistors using a crystalline silicon film as the active layer have such a tendency that the electrical characteristic is shifted to the depletion direction (negative side) in n-type transistors and to the enhancement direction (negative side) in p-type transistors. The reason for this tendency is considered the difference in work function between the gate electrode and the active layer that depends on the conductivity type.
FIG. 2
schematically shows the above-mentioned electrical characteristics (Id-Vg characteristics) of transistors. The horizontal axis represents the gate voltage Vg and the vertical axis represents the vertical axis represents the drain current Id. Reference numerals
201
and
202
denote Id-Vg characteristics of an n-type transistor and a p-type transistor, respectively. Intersections of the horizontal axis and the Id-Vg characteristics
201
and
202
indicate threshold voltages.
Reference numeral
203
denotes a window width Vwin which is defined as a difference between a threshold voltage V
th, n
of the n-type transistor and a threshold voltage V
th, p
of the p-type transistor, i.e., V
th, n
−V
th, p
. Further, reference numeral
204
denotes a window center Vcen which is defined as a value at the center of the window, i.e., (½)(V
th, n
+V
th, p
).
In conventional CMOS circuits, since the window width Vwin is shifted to the negative side, the window center Vcen is smaller than 0 V. The above-mentioned publication No. Hei. 4-206971 points out that deviations of output voltages due to the difference between the threshold voltages cause deterioration in the characteristics of a CMOS circuit.
One method for solving this problem is to control the threshold voltages by adding, to the channel forming regions, an impurity (phosphorus or boron) that imparts one conductivity type (hereinafter called “channel doping method”). However, this method has a problem that impurity ions cause carrier scattering, possibly reducing the operation speed.
In particular, in the deep submicron range in which the channel length is as short as 0.01-0.1 &mgr;m, only one to several impurity ions exist in the channel region. There is a report that the existence of impurity ions drastically changes the electrical characteristics.
It is now necessary to refer to a short channel effect preventing technique (pinning technique) that is proposed by the present inventors. This technique will be outlined below with reference to
FIGS. 3A-3C
. Although
FIGS. 3A-3C
show a thin-film transistor formed on an insulative substrate, the same things apply to a transistor formed within a semiconductor substrate.
The short channel effect is a generic term representing such phenomena as a reduction in breakdown voltage due to the punch-through phenomenon and deterioration of the subthreshold characteristic. These phenomena are caused such that the drain-side depletion layer expands to the source region to establish a situation that carriers cannot be controlled only by the gate voltage.
The pinning technique is a technique for preventing the expansion of the drain-side depletion layer by providing, artificially and locally, impurity regions in the channel forming region. The inventors use the term “pinning” as meaning “preventing.”
Specifically, the active layer of a transistor is configured as shown in
FIGS. 3A-3C
. In
FIG. 3A
, reference numerals
301
-
303
denote a source region, a drain region, and a channel forming region, respectively. Impurity regions
304
are artificially formed in the channel forming region
303
. In the channel forming region
303
, regions
305
other than the impurity regions
304
are substantially intrinsic regions where carriers are allowed to move. Symbols L and W denote a channel length and a channel width, respectively.
The impurity regions
304
are obtained by forming a fine pattern by an electron beam lithography method or the like. Although
FIG. 3A
shows an example in which the impurity regions
304
are formed in a linear pattern, they may be formed in a dot pattern.
FIG. 3B
is a sectional view taken along line A-A′ in FIG.
3
A. Reference numeral
306
denotes a substrate having an insulative surface.
FIG. 3C
is a sectional view taken alone line B-B′ in FIG.
3
A.
The impurity regions
304
, which are disposed in the channel forming region
303
, form regions (energy barriers) where the diffusion potential is locally high in the channel forming region
303
. The energy barriers can effectively prevent (i.e., pin) the drain-side depletion layer from expanding toward the source side.
Sufficiently high energy barriers can be formed by adding any of oxygen, nitrogen, and carbon. B (boron) and P (phosphorus) may be added in the cases of an n-tvpe transistor and a p-type transistor, respectively.
With the above structure, it is expected that a reduction in threshold voltage as one aspect of the short channel effect can be prevented effectively. Naturally, it is also possible to prevent a reduction in breakdown voltage due to the punch-through phenomenon and deterioration of the subthreshold characteristic.
It is expected that the structure of
FIGS. 3A-3C
causes a narrow channel effect separately from the above effects. That is, a narrow channel effect can be caused artificially in the carrier movement regions
305
by sufficiently narrowing the intervals between the impurity regions
304
.
As described above, the pinning technique that is proposed by the inventors is effective in such a range as covers device elements in which the short channel effect occur (channel length: 2 &mgr;m or less) and finer device elements in the deep submicron range (channel length: 0.01-0.1 &mgr;m).
However, the shift of the window center Vcen due to the difference in work function between the gate electrode and the active layer that was described above in the conventional example (
FIG. 2
) similarly occurs even if the pinning technique is employed. Therefore, in the submicron range, it is necessary to control the threshold voltages while preventing the short channel effect.
SUMMARY OF THE INVENTION
An object of the present invention is to correct a difference in threshold voltage by a method other than the channel doping method in a CMOS circuit that is miniaturized to such an extent that the short channel effect occurs (channel length: 0.01-2 &mgr;m).
In other words, an object of the invention is to provide a technique for making the window center Vcen as close to 0 V as possible, that is, for controlling the threshold voltages of n-channel and p-channel semiconductor devices so that their absolute values are substantially equalized.
The main point of the invention is to balance the threshold voltages Vth of a CMOS circuit, that is, to correct a difference therebetween, by utilizing the short channel effect (SCE) and the narrow channel effect (NCE) that occur as device elements are miniaturized.
According to the invention, there is provided a semiconductor device having a CMOS structure in which an n-channel semiconductor device and a p-channel semiconductor device are combined complementarily, comprising first means provided in the n-channel semiconductor, for strengthening a narrow channel effect; and second means provided in the p-channel semiconductor, for strengthening a short channel effect, wherein the first and second means are provided so as to make absolute values of threshold voltages of the n-channel and p-channel semiconductor devices appro
Fish & Richardson P.C.
Ho Tu-Tu
Nelms David
Semiconductor Energy Laboratory Co,. Ltd.
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