Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-05-28
2004-12-07
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S324000, C257S325000, C257S410000, C257S411000
Reexamination Certificate
active
06828619
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device and, more particularly, to a metal oxide nitride oxide semiconductor (MONOS) type of nonvolatile semiconductor storage device.
2. Description of the Prior Art
There are two major types of nonvolatile storage elements formed as MIS transistors: those using the metal nitride oxide semiconductor (MNOS) type transistor, and those using the floating gate (FG) type transistor.
In the MNOS type element, information charge is accumulated in an interfacial region or the like formed in a boundary region in a two-layer insulating film. Elements of this type include those called MONOS having a silicon oxide film on a silicon nitride film, and also include those having various combinations of insulating films other than this combination of silicon oxide film and silicon nitride film.
The FG type element has a two-layer gate electrode structure in which information charge is accumulated on a floating gate electrode, which is a first gate electrode. In this structure, the first gate electrode is formed in a floating state on a silicon oxide film on a major surface of a semiconductor substrate, an interlayer insulating film in which a silicon oxide film and a silicon nitride film are combined is provided on the first gate electrode, and a second gate electrode, which is a control gate electrode, is formed on the interlayer insulating film. The first gate electrode is covered with the second gate electrode.
Basically, nonvolatile memories called “flash memory” can use the above-mentioned M(O)NOS transistor or the FG transistor as their nonvolatile storage element. In all the current mass-produced flash memories, however, only FG transistors are used as a nonvolatile storage element. However, the information charge holding characteristic of FG transistors theoretically recognized is not satisfactorily high, and there is a need to use a silicon oxide film having a comparatively large thickness of 9 nm or more as a tunnel oxide film between the semiconductor substrate major surface and the floating gate electrode. Therefore there is a limit to the reduction in the voltage for write/erase of information charge.
On the other hand, in MNOS transistors, the film thickness of the tunnel oxide film between the semiconductor substrate major surface and the silicon nitride film can easily be reduced, and a thin silicon oxide film of 3 nm or less can be used. Therefore, it is theoretically possible to reduce the operating voltage, particularly the voltage for write/erase of information charge. Operations for writing and erasing information charge in this type of nonvolatile storage element are as described below. That is, in MNOS transistors, information charge is written by injecting electrons from the semiconductor substrate into the above-mentioned interfacial region through a direct tunnel in a silicon oxide film about 2 nm thick formed on the semiconductor substrate major surface, and information charge is erased by a reverse operation, i.e., releasing electrons from the interfacial region to the semiconductor substrate. Such an interfacial region is formed of as an electron capture region. The written state of information charge in such a region corresponds to stored information “1”, and the information charge erased state corresponds to stored information “0”. In recent years, various studies have been energetically made for the purpose of putting M(O)NOS transistors theoretically considered capable of reducing the write/erase voltage to practical use as a storage element in nonvolatile memories such as flash memories.
For example, U.S. Pat. No. 5,768,192 discloses the basic structure of a nonvolatile storage element, which is an instance of a MONOS transistor used as a nonvolatile storage element in a flash memory. U.S. Pat. No. 5,966,603 recently made public discloses a technique relating to a nitride read only memory (NROM) as a technique enabling a nonvolatile memory manufacturing process to be advantageously simplified (hereinafter referred to as “first conventional art”). The basic structure of the nonvolatile memory according to this art is the same as that disclosed in above described U.S. Pat. No. 5,768,192.
Further, the structure of a nonvolatile storage element proposed in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123 (hereinafter referred to as “second conventional art”) is known.
The first conventional art will be described with reference to
FIGS. 21
to
24
. The basic operation of the above-described MONOS will also be described.
FIG. 21
is a plan view of a cell array of an NROM.
FIGS. 22A
to
22
D are cross-sectional views taken along the line X—X shown in FIG.
21
.
FIGS. 22A
to
22
D show process steps for manufacturing the NROM. Description with reference to
FIG. 21
will be made only of wiring in the cell array for ease of understanding.
In the cell array of the NROM, as shown in
FIG. 21
, a first diffusion layer
102
, a second diffusion layer
103
, a third diffusion layer
104
, and so on are formed on a silicon substrate
101
, and word lines (gate electrodes)
105
,
106
, and
107
are arranged perpendicularly to the diffusion layers. The diffusion layers form bit lines.
As shown in
FIG. 22A
, a first insulating film
108
is formed by thermal oxidation of a P-conduction type of silicon substrate
101
, and a silicon nitride film is formed as a second insulating film
109
by chemical vapor deposition (CVD). After this film forming, a resist mask
110
having a diffusion layer pattern, which is a plan pattern of strips (strip pattern), is formed on the second insulating film
109
by a well-known lithography technique. The second insulating film
109
is then removed by etching. Thereafter, as shown in
FIG. 22B
, ions of an n-type impurity such as arsenic are implanted by using the resist mask
110
as anion implantation mask, and the resist mask
110
is removed, followed by a heat treatment. The first diffusion layer
102
, the second diffusion layer
103
and the third diffusion layer
104
are thus formed in the surface of the silicon substrate
101
.
Subsequently, the entire surface is subjected to thermal oxidation at a temperature of 750° C. or higher. As shown in
FIG. 22C
, a non-diffusion-layer insulating film
111
having a thickness of 100 nm is formed by this thermal oxidation on the surfaces of the first diffusion layer
102
, the second diffusion layer
103
and the third diffusion layer
104
. When this thermal oxidation is performed, the surface of the second insulating film
109
is also thermally oxidized to form a silicon oxide film as a third insulating film
112
. Thus, a laminated insulating film of ONO structure constituted by the third insulating film
112
(silicon oxide film), the second insulating film
109
(silicon nitride film) and the first insulating film
108
(silicon oxide film) is formed.
Subsequently, a tungsten polycide film having a film thickness of about 200 nm is deposited as an electroconductive film on the entire surface and is processed by well-known lithography and dry etching techniques to form the word line
105
.
Thus, as shown in
FIG. 22D
, bit lines for NROM cells are formed on the silicon substrate
101
by the first diffusion layer
102
, the second diffusion layer
103
, the third diffusion layer
104
, and so on; information charge write/erase regions are formed by the first insulating film
108
, the second insulating film
109
and the third insulating film
112
formed in the ONO structure; and the word lines
105
,
106
, and
107
, also shown in
FIG. 21
, are arranged. A basic NROM cell structure is thus formed.
The basic operation of the MONOS transistor having the above-described NROM cell basic structure will be described. An operation for writing information charge (electrons in this case) is as described below. As shown in
FIG. 23A
, the silicon substrate
101
and the first diffusion layer
102
, for example, are fixed at ground potentia
NEC Electronics Corporation
Prenty Mark V.
Young & Thompson
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