Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-11-09
2004-02-24
Whitmore, Stacy A (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S013000
Reexamination Certificate
active
06698000
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor process parameter determining method, a semiconductor process parameter determining system, and a semiconductor process parameter determining program used for determining a process parameter in a semiconductor device manufacturing method.
2. Description of Related Art
FIG. 18
is a flow chart showing an example of conventional semiconductor process parameter determining methods. Here, the process parameters determined by the conventional semiconductor process parameter determining method shown in
FIG. 18
are two types of parameters, a wiring width and a wire spacing in a semiconductor device.
First of all, in Step ST
101
, TEG (Test Element Group) for evaluation is designed by letting the wiring width be a parameter. For instance, five types of TEGs in which the wiring widths are 1 &mgr;m, 2 &mgr;m, 4 &mgr;m, 7 &mgr;m, and 10 &mgr;m are designed. Subsequently, in Step ST
102
, the designed TEGs are manufactured by use of a semiconductor process technology. Then, in Step ST
103
, the optimum wiring width is determined by evaluating the five types of manufactured TEGs.
For instance, if 4 &mgr;m is the optimum wiring width, in Step ST
104
TEGs for evaluation are designated by fixing the wiring width to 4 &mgr;m, and letting the wire spacing be a parameter. For example, five types of TEGs in which the wire spacings are 1 &mgr;m, 2 &mgr;m, 3 &mgr;m, 4 &mgr;m, and 5 &mgr;m are designed. Then, in Step ST
105
the designed TEGs are manufactured by use of a semiconductor process technology. After that, in Step ST
106
, the optimum wire spacing is determined by evaluating the five types of manufactured TEGs.
Since the conventional semiconductor process parameter determining method is constructed as mentioned above, a plurality of TEGs should be designed, manufactured, and evaluated in order to determine one process parameter. As a result, since much time is spent in determining the process parameter, there is a drawback that the efficiency is extremely low and the cost used until the determination of the process parameter is extremely high.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the above-mentioned drawback. An object of the present invention is to provide a semiconductor process parameter determining method, a semiconductor process parameter determining system, and a semiconductor process parameter determining program that promptly determine the optimum process parameter, and hold down the cost thereof.
According to a first aspect of the present invention, there is provided a semiconductor process parameter determining method, comprising the steps of: inputting a first process parameter as an input parameter; obtaining a predetermined circuit characteristic by performing a simulation on a gate level and/or a transistor level by use of the input parameter with a second process parameter of each wiring layer constructing a semiconductor device as a variable; determining whether said simulation is completed or not; extracting the second process parameter for each wiring layer obtaining a desired circuit characteristic; and outputting the extracted, second process parameter for each wiring layer.
Here, the input parameter may include a tolerance, which is selected from an operation frequency, a cross talk noise tolerance, a power consumption tolerance, a transition delay tolerance, and the maximum allowable number of wiring layers.
The method may further comprise a step of converting the tolerance into any one of inductance, capacitance and resistance.
When the input parameter includes a tolerance and the first process parameter includes floorplan information and a netlist, the method may comprise a step of format-converting the floorplan information and netlist while executing the placement and routing based on the tolerance.
According to a second aspect of the present invention, there is provided a semiconductor process parameter determining system, comprising: a terminal including an input means for inputting a first process parameter and/or a tolerance, an output means for outputting a received, second process parameter for each wiring layer constructing a semiconductor device, and a communicating means capable of sending and receiving the first process parameter, the tolerance, and the second process parameter through a communication line; and a semiconductor process parameter determining apparatus that obtains a predetermined circuit characteristic by executing a simulation based on the first process parameter and/or the tolerance received from the terminal, and sends the second process parameter for each wiring layer performing a desired circuit characteristic based on the results of the simulation to the terminal.
Here, the semiconductor process parameter determining apparatus may charge each terminal for use according to information amount and a type of information where the information is sent and received from/to each terminal.
According to a third aspect of the present invention, there is provided a semiconductor process parameter determining program capable of executing by computer a semiconductor process parameter determining method comprising the steps of: inputting a first process parameter and/or a tolerance as an input parameter; obtaining a predetermined circuit characteristic by means of simulation on a gate level and/or a transistor level by use of the input parameter with a second process parameter for each wiring layer constructing a semiconductor device as a variable; determining whether the simulation is completed or not; extracting the second process parameter for each wiring layer accomplishing a desired circuit characteristic; and outputting the extracted, second process parameter for each wiring layer.
Here, the first process parameter may be selected from gate scale, an in-the-same-layer wiring adjacent probability, a between-different-layers wiring overlapping probability, the number of wiring layer, library information, a plurality of wiring materials, a plurality of via materials, floorplan information, and a netlist.
The tolerance may be selected from an operation frequency, a cross talk noise tolerance, a power consumption tolerance, a transition delay tolerance, the maximum allowable number of wiring layer.
The second process parameter may be selected from a wiring width, a wire spacing, and a conductor thickness of the wiring layer, a relative dielectric constant and a film thickness of a dielectric, a plurality of wiring materials, a plurality of via materials, and a plurality of numbers of wiring layer.
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Mehmet, Aktuma, et al., 1998, ACM, pp. 57-64.
Mitsubishi Denki & Kabushiki Kaisha
Whitmore Stacy A
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