Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-25
2004-12-28
Thomas, Tom (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S348000, C257S349000, C257S350000, C257S352000, C257S354000
Reexamination Certificate
active
06835983
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuit (IC) chips, and more particularly to a silicon-on-insulator (SOI) IC chip that comprises a top Si-containing layer (i.e., the SOI layer), in which Si devices are formed, that has regions of different thickness. Since the optimal silicon thickness for various SOI devices are different, the present invention enables silicon devices requiring different SOI silicon thickness to be integrated on the same chip.
BACKGROUND OF THE INVENTION
Conventional SOI IC chips, independent on how the SOI material is prepared, has one starting silicon thickness. The silicon thickness is determined by the specific silicon device to be built. For example, for so-called partially-depleted CMOS devices, the silicon layer thickness should be thick enough, typically on the order of about 100 to about 300 nm, such that there is always a non-depleted quasi-neutral silicon region left beneath the CMOS device channel region, or in the CMOS “device substrate”. However, for so-called fully depleted CMOS devices, the silicon layer thickness should be thin enough, typically on the order of about 10 to about 150 nm, such that the “device substrate” beneath the gate region is normally depleted of mobile carriers and there is no quasi-neutral region left beneath the CMOS device channel region.
One serious limitation with conventional single-thickness SOI material is that it is not suitable for building several kinds of silicon devices, or silicon devices for different applications, on the same chip. For example, high-speed digital CMOS usually uses a relatively thin Si layer, while analog CMOS prefers a thicker Si layer. In fact, for precision analog circuits, it is preferred to have the silicon layer thick enough to provide a convenient device substrate contact in order to avoid undesirable floating-body effects associated with SOI MOSFET devices without device substrate contact. Moreover, bipolar devices may require an even thicker silicon layer in order to accommodate the three vertical device regions, namely the emitter, the base and the collector.
In view of the above, there is a need for providing SOI IC chips in which the top Si-containing layer of the SOI wafer has regions of variable thickness. By providing regions of different thickness on the same Si layer, a SOI wafer suitable for integrating various types of silicon devices on the same SOI chip can be obtained. That is, it also permits “system on an SOI chip” to be realized.
SUMMARY OF THE INVENTION
The present invention provides SOI materials which comprise a top Si-containing layer (i.e., an SOI layer) which includes regions having variable thickness. Specifically, the inventive SOI material comprises:
a buried insulating region which is sandwiched between a bottom Si-containing layer and a top Si-containing layer, said top Si-containing layer comprises at least one region of a first thickness and at least one other region of a second thickness wherein said first thickness is different from said second thickness.
The present invention also provides various SOI integrated circuit chips which include at least the inventive SOI material on which various devices such as CMOS transistors and bipolar transistors are formed.
The present invention also relates to a method of fabricating the above mentioned SOI material. Specifically, the method of the present invention comprises the steps of:
providing a starting SOI wafer which comprises a buried insulating region sandwiched between a bottom Si-containing layer and a top Si-containing layer, said top Si-containing layer having a substantially uniform thickness; and
thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon.
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patent: 2001/0008284 (2001-07-01), Huang
Ning Tak H.
Sadana Devendra K.
Fenty Jesse A.
Scully Scott Murphy & Presser
Thomas Tom
Trepp Robert M.
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