Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2001-08-28
2004-12-21
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S105000
Reexamination Certificate
active
06834334
ABSTRACT:
BACKGROUND
The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and apparatus for address decoding of embedded DRAM (eDRAM) devices.
As a result of the package/pin limitations associated with discrete, self-contained devices such as DRAMs, memory circuit designers have used certain multiplexing techniques in order to access the large number of internal memory array addresses through the narrow, pin-bound interfaces. Because these discrete DRAMs have been in use for some time, a standard interface has understandably emerged over the years for reading and writing to these arrays.
More recently, embedded DRAM (eDRAM) macros have been offered, particularly in the area of Application Specific Integrated Circuit (ASIC) technologies. For example, markets in portable and multimedia applications such as cellular phones and personal digital assistants utilize the increased density of embedded memory for higher function and lower power consumption. Unlike their discrete counterparts, the eDRAM devices do not have the limited I/O pin interfaces with associated memory management circuitry. In fact, the typical I/O counts for eDRAM devices can number in the hundreds.
Another possible use for the newer eDRAM devices would be the ability to use them interchangeably with existing SDRAM modules, thereby forming a structure utilizing a standard SDRAM interface, but having an embedded memory module therein. Unfortunately, the memory array configurations for a standard SDRAM and an eDRAM are somewhat different. In addition, the existing multiplexing and addressing schemes used by a memory manager (e.g., a hard disk controller) are not suited for use with an eDRAM structure, particularly with regard to the addressing of the array. For example, the limited I/O pin interfaces in SDRAM memory management circuitry have resulted in the use of a “time shared” addressing method, wherein a row address is presented at an initial clock cycle and held in a register until the corresponding column address is presented at a later clock cycle. The eDRAM devices, on the other hand, do not make use of these time shared addressing techniques.
BRIEF SUMMARY
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for decoding a memory array address for an embedded DRAM (eDRAM) device, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.
In a preferred embodiment, a first subset of the initial address bits is used generate said translated column address bits, and a second subset of initial address bits is used to identify a specific location within an eDRAM column corresponding to the translated column address bits. The SDRAM memory manager processes memory address information in accordance with a first memory page structure, while the eDRAM device is configured in accordance with a second memory page structure. A memory page structure is defined by the number of columns included in a given row, and the number of storage locations located at each column in the given row. The first memory page structure and the second memory page structure contain an unequal number of columns and an equal number of storage locations therein.
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Corti William D.
Marsh Joseph O.
Won Michael
Choi Woo H.
International Business Machines - Corporation
Kim Matthew
Walsh Robert A.
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