Plated metal transistor gate and method of formation

Details Plated metal transistor gate and method of formation Plated metal transistor gate and method of formation

2003-03-31

2004-02-03

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S648000, C438S656000, C438S683000, C438S686000, C257S750000, C257S761000, C257S763000, C257S764000

Reexamination Certificate

active

06686282

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to making integrated circuits having metal gates, and more particularly to forming them by plating.
RELATED ART
As semiconductor devices continue to scale down in geometry, the conventional polysilicon gate is becoming inadequate. One problem is relatively high resistivity and another is depletion of charge near the interface between the polysilicon gate and gate dielectric. To overcome these deficiencies of polysilicon, metal gates are being pursued as an alternative. The deposition of metal gates, however, has also presented problems. One technique for the deposition is physical vapor deposition (PVD), but this technique results in plasma induced damage to the gate dielectric. Chemical vapor deposition (CVD) is another technique but that tends to result in impurities in the gate dielectric that cause degradation of the quality of the gate dielectric. A resulting problem is increased current leakage through the gate dielectric. Plasma enhanced chemical vapor deposition (PECVD) is another alternative, but it also causes the plasma damage in the manner that PVD does.
Thus, there is a need for a technique of forming metal gates in which the technique is manufacturable and avoids the problems associated with PVD, CVD, and PECVD.


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