Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-07-20
2004-12-07
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000, C711S143000
Reexamination Certificate
active
06829683
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to multi-processor computer systems and more particularly to a system and method for transferring ownership of data in a distributed shared memory system.
BACKGROUND OF THE INVENTION
Complications exist in transferring ownership of data between processors of different nodes. In a snoopy processor bus system, implicit writebacks are generated each time a processor obtains control of data that has been previously modified. These implicit writebacks cause the delay in the transfer of ownership to the data. Therefore, it is desirable to maintain efficient cache line ownership transitions between nodes.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated by those skilled in the art that a need has arisen for a technique to efficiently transfer ownership of data without undue delay. In accordance with the present invention, a system and method for transferring ownership of data in a distributed shared memory system are provided that substantially eliminate or greatly reduce disadvantages and problems associated with conventional ownership transfer techniques.
According to an embodiment of the present invention, there is provided a method for transferring ownership of data in a distributed shared memory system that includes generating a return request at a first processor to return a modified cache line. In the meantime, a read request for the cache line is received at a memory directory associated with a home memory for they cache line from a second processor. The return request is forwarded from a processor interface associated with the first processor to the memory directory. The memory directory generates an intervention request that is forwarded to the processor interface. The processor interface provides an intervention response to the intervention request to the second processor prior to processing of the return request, the response including the cache line.
The present invention provides various technical advantages over conventional ownership transfer techniques. For example, one technical advantage is to transfer ownership without performing serial ownership processing. Another technical advantage is to directly transfer ownership of a cache line without involving the memory directory associated with the home memory for the cache line. Another technical advantage is to effectively process latent writebacks after an ownership transition of a cache line. Other advantages may be readily apparent to those skilled in the art from the following figures, description, and claims.
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Baker Paul
Baker & Botts L.L.P.
Bragdon Reginald G.
Silicon Graphics Inc.
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