Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-23
2004-10-26
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S324000, C257S411000
Reexamination Certificate
active
06809385
ABSTRACT:
Japanese Patent Application No. 2001-21930, filed on Jan. 30, 2001, is hereby incorporated by reference in its entirety.
BACKGROUND
1. Technical Field
The present invention relates to a semiconductor integrated circuit device including nonvolatile semiconductor memory devices.
2. Related Art
As one type of nonvolatile semiconductor memory device, a MONOS (Metal Oxide Nitride oxide Semiconductor) memory device is known. In the MONOS memory device, a gate insulating layer disposed between a channel and a gate is formed of a laminate consisting of two silicon oxide layers and a silicon nitride layer, and charges are trapped in the silicon nitride layer.
A device shown in
FIG. 16
is known as such a MONOS nonvolatile semiconductor memory device (Y. Hayashi, et al., 2000
Symposium on VLSI Technology Digest of Technical Papers
, 122-123).
In this MONOS memory cell
100
, a word gate
14
is formed on a semiconductor substrate
10
with a first gate insulating layer
12
interposed. A first control gate
20
and a second control gate
30
are disposed on either side of the word gate
14
in the shape of sidewalls. A second gate insulating layer
22
is present between the bottom of the first control gate
20
and the semiconductor substrate
10
. A side insulating layer
24
is present between the side of the first control gate
20
and the word gate
14
. A second gate insulating layer
32
is present between the bottom of the second control gate
30
and the semiconductor substrate
10
. A side insulating layer
34
is present between the side of the second control gate
30
and the word gate
14
. Impurity diffusion layers
16
and
18
forming a source region or a drain region are formed in the semiconductor substrate
10
in a region between the control gate
20
and the control gate
30
facing each other in adjacent memory cells.
As described above, one memory cell
100
includes two MONOS memory elements, one on each side of the word gate
14
. These MONOS memory elements can be controlled separately. Therefore, the memory cell
100
is capable of storing 2 bits of information.
This MONOS memory cell operates as follows. One of the control gates of the memory cell
100
is capable of selecting read or write operation separately by biasing the other control gate to an override voltage.
A write (program) operation is described below with reference to a case where electrons are injected into the second gate insulating layer (ONO film)
32
at the left in CG [i+1] in FIG.
16
. In this case, the bit line (impurity diffusion layer)
18
(D[i+1]) is biased to a drain voltage of 4 to 5 V. The control gate
30
(CG[i+1]) is biased to 5 to 7 V in order to cause hot electrons to be injected into the second gate insulating layer
32
at the left of the control gate
30
(CG[i+1]). A word line connected to the word gates
14
(Gw[i] and Gw[i+1]) is biased at a voltage slightly higher than the threshold value of the word gate in order to limit the program current to a specific value (10 &mgr;A or less). The control gate
20
(CG[i]) is biased to an override voltage. This override voltage enables a channel under the control gate
20
(CG[i]) to conduct irrespective of the memory state. A left side bit line
16
(D[i]) is biased to ground. Control gates and diffusion layers in unselected memory cells are grounded.
In an erase operation, stored charges (electrons) are erased by injection of hot holes. Hot holes can be generated by B—B tunneling at the surface of the bit diffusion layer
18
. At this time, the voltage Vcg of the control gate is biased to a negative voltage (−5 to −6 V) and the voltage of the bit diffusion layer is biased to 5 to 6 V.
In the above-cited reference, according to the MONOS memory cell, two separately controllable programming sites in a single memory cell can provide bit density of 3F
2
.
SUMMARY
According to one embodiment of the present invention, there is provided a semiconductor integrated circuit device having a memory cell array in which nonvolatile semiconductor memory devices are arranged in a matrix with a plurality of rows and columns,
wherein each of the nonvolatile semiconductor memory devices comprises:
a word gate formed on a semiconductor layer with a first gate insulating layer interposed;
an impurity diffusion layer which forms either a source region or a drain region; and
first and second control gates in the shape of sidewalls formed along either side of the word gate, wherein:
the first control gate is disposed on the semiconductor layer with a second gate insulating layer interposed, and also on the word gate with a side insulating layer interposed;
the second control gate is disposed on the semiconductor layer with another second gate insulating layer interposed, and also on the word gate with another side insulating layer interposed;
the first and second control gates extend in a first direction; and
a pair of the first and second control gates, adjacent in a second direction which intersects the first direction, is connected to a common contact section.
According to this semiconductor integrated circuit device, since every pair of the control gates in the shape of sidewalls is connected to the common contact section, electrical connection with narrow control gates can be achieved reliably.
The semiconductor integrated circuit device of the present invention has the following features.
(A) Each of the first and second control gates may be formed of a conductive layer extending in the direction in which the impurity diffusion layer extends.
(B) The common contact section may be formed in the same step as the first and second control gates, be connected to the first and second control gates, and include a conductive layer formed of the same material as the first and second control gates.
(C) The common contact section may include an insulating layer formed on the semiconductor layer, a conductive layer formed on the insulating layer, and a cap layer formed on the conductive layer. The insulating layer may be formed by the same step as the side insulating layer located between the word gate and the control gate, and may be formed of a laminate consisting of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.
(D) The side insulating layers may be located between the word gate and the first and second control gates; and the upper ends of the side insulating layers may be located higher than the first and second control gates with respect to the semiconductor layer. This enables a buried insulating layer which covers the control gates to be formed reliably. Specifically, the buried insulating layer may be formed between the two side insulating layers disposed in contact with the first and second control gates; and the buried insulating layer may cover the adjacent first and second control gates.
(E) The common contact section may be provided in contact with one end of the impurity diffusion layer. The common contact sections may be provided alternately on one end and the other end of a plurality of impurity diffusion layers.
(F) The memory cell array may be divided into a plurality of blocks; and the impurity diffusion layers in blocks adjacent to each other in the first direction may be connected to each other through a contact impurity diffusion layer formed in the semiconductor layer.
(G) The second gate insulating layer may be formed of a laminate consisting of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. The side insulating layer may be located between the word gate and the control gate, and be formed of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.
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patent: 5883001 (1999-03-01), Jin et al.
patent: 5891775 (1999-04-01), H
Ebina Akihiko
Maruo Yutaka
Pham Long
Pizarro-Crespo Marcos D.
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