Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-14
2004-03-30
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S412000
Reexamination Certificate
active
06713824
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device constituted of an integrated circuit having a MOS transistor formed therein, and more particularly, to a method of forming a gate electrode for improving reliability of a gate insulating film of the MOS transistor.
Now, we will explain steps of manufacturing the MOS transistor which serves as a constitutional element of an integrated circuit formed on a conventional semiconductor substrate, by taking an NMOS transistor having an LDD (lightly doped drain) structure, as an example. First, an element isolating region
2
is formed on a surface region of a p-type silicon semiconductor substrate
1
by a LOCOS method or the like. A gate insulating film (SiO
2
)
3
is formed on an element region surrounded by the element isolating region
2
. Then, boron ions are injected (channel ion injection) over an entire main surface of the semiconductor substrate
1
to control a threshold voltage (FIG.
9
A). Subsequently, a polysilicon film is deposited over the entire main surface of the semiconductor substrate
1
and patterned to form a gate electrode
4
of polysilicon (PolySi) on the gate insulating film
3
in the element region. Thereafter, P (phosphorus) ions are injected in a low amount to form an n
−
source/drain region
5
for mitigating a high electric field (FIG.
9
B).
Next, a silicon oxide film (SiO
2
)
6
is deposited on the semiconductor substrate
1
by a CVD (Chemical Vapor Deposition) method or the like so as to cover the gate electrode
4
(FIG.
10
A). Subsequently, the silicon oxide film
6
is anisotoropically etched to form a side wall insulating film
7
on a side wall of the gate electrode
4
. Thereafter, n-type impurity ions such as arsenic (As) ions are doped in a high amount to form an n
+
source/drain region
8
(FIG.
10
B).
As described above, in the MOS transistor, a polysilicon film doped with phosphorus, arsenic, or boron is generally used as the gate electrode. The polysilicon film is deposited by an LPCVD method at a reaction-chamber ambient temperature of about 600° C. The polysilicon film deposited under the aforementioned conditions has a film stressfilm stress of 300 MPa or more despite the presence or absence of a dopant. Such a high stress of the gate electrode is applied to a gate insulating film (in this prior art, the film may be composed of a silicon oxide film, hereinafter simply called “gate insulating film”, for the simplicity of explanation) whereby the high stress affects reliability of the gate insulating film or gate insulating film formed under the gate electrode. To explain more specifically, when the stress is applied to the gate insulating film, the bonding between silicon and oxygen constituting the gate insulating film is distorted. As a result, the bonding tends to be easily broken, readily inducing dielectric breakdown of the gate insulating film.
When intrinsic dielectric breakdown of the insulating film takes place, the total amount Qbd of electric charge passing through the insulating film is up to about 15 C/cm
2
under application of an electric field of 12 MV/cm to the insulating film, assuming that the thickness of the insulating film is about 10 nm. The total charge amount Qbd is a value on the basis of which the reliability of a transistor is determined. Therefore, the Qbd desirably has a large value. Particularly, in non-volatile storage device, such as EEPROM (Electrically Erasable Programmable Read Only memory) in which data is written into a memory cell by using a tunnel current, how many times the device can be programmed is restricted by the total charge amount Qbd. Therefore, it is necessary to increase the total charge amount Qbd in order to improve performance of the device.
BRIEF SUMMARY OF THE INVENTION
The present invention was made in view of the aforementioned circumstances. The present invention provides a semiconductor device and a method of manufacturing the same, improved in reliability of a gate insulating film and increased in its total charge amount Qbd by suppressing a film stress of a gate electrode formed of a polysilicon film, to a low value.
Since the film stress of a gate electrode is closely related with a film formation temperature, it is possible to reduce the film stress lower than in the conventional case, by forming a film at as a high temperature as 640° C. or more, preferably 650° C. or more. With a decrease in the film stress of the gate electrode at this time, the total charge amount Qbd of a gate insulating film underlying the gate electrode increases, with the result that reliability not only of the gate insulating film but also a semiconductor device including the gate insulating film is improved.
More specifically, the semiconductor device of the present invention comprises
a semiconductor substrate;
source/drain regions formed on the semiconductor substrate;
a gate insulating film formed between the source/drain regions on the semiconductor substrate; and
a gate electrode formed on the gate insulating film,
in which
a film stress of the gate electrode is 200 MPa or less in terms of absolute value.
The gate electrode may be a polysilicon film and may be in contact with the gate insulating film.
A metal silicide film or a high-melting point metal film may be formed on the polysilicon film. In other words, the gate electrode may be formed of the polysilicon film and the metal silicide film or the high melting point metal film. Furthermore, the high melting point metal film is formed on the metal silicide film, and therefore, the gate electrode may be formed of the polysilicon film, the metal silicide film, and the high melting point metal film.
A MOS transistor having the source/drain regions, the gate insulating film, and the gate electrode, may be adopted in a non-volatile semiconductor storage device such as an EEPROM. When the MOS transistor according to the invention is used in an EEPROM, the programmable number can be increased since a total charge amount Qbd of electric charge passing through the gate insulating film serving as a floating gate has a direct effect upon characteristics of a device.
According to the present invention, there is provided a method of manufacturing a semiconductor device, according to the present invention comprises the steps of:
forming source/drain regions in a semiconductor substrate;
forming a gate insulating film between the source/drain regions on the semiconductor substrate; and
forming a gate electrode including a polysilicon film on the gate insulating film and having a film stress of 200 MPa or less;
in which
the polysilicon film is formed by depositing polysilicon on the gate insulating film by a CVD method at a temperature of 640° C. or more. Preferably, the temperature at which a gate insulating film is formed may be 650° C. or more, in order to stably provide a gate electrode whose film stress is 200 MPa or less.
The polysilicon film may be formed while the semiconductor substrate is rotated at a high speed. In this manner, it is possible to form a uniform film on a semiconductor substrate.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
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Akahori Hiroshi
Katsui Shuji
Mikata Yuuichi
Eckert George
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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