Method and circuit for reading data from a ferroelectric...

Details Method and circuit for reading data from a ferroelectric... Method and circuit for reading data from a ferroelectric...

2002-09-20

2004-12-21

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S203000

Reexamination Certificate

active

06834006

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric memory, and more particularly to a method and circuit for reading data from a ferroelectric memory.
2. Description of the Related Art
A ferroelectric memory is a semiconductor device that stores data in ferroelectric capacitors.
FIG. 6
shows one ferroelectric memory cell Mfe and its associated circuits in a conventional ferroelectric memory. The associated circuits include a bit-line driver BLDu, a plate-line driver PLDu, a sense amplifier SA, and a control circuit CTLu.
The memory cell Mfe comprises a ferroelectric capacitor CFe and a selection transistor SLTr connected in series between a bit line BL and a plate line PL. A ferroelectric memory cell of this type, having a single transistor and a single capacitor, is referred to as a 1T1C memory cell. The ferroelectric capacitor can be positively or negatively polarized by an applied voltage, and the polarization remains after the voltage is removed, enabling information to be stored in a nonvolatile manner. The stored information is read by placing the bit line BL in an electrically floating state, manipulating the plate-line potential, and comparing the bit-line potential with a reference potential.
Many previous ferroelectric memories used dummy ferroelectric capacitors to generate reference potentials precisely matched to the electrical characteristics of different memory cells. Japanese Unexamined Patent Application Publication No. 11-260066 (referred to below as the prior art) describes a method of reading information from a 1T1C ferroelectric memory cell without the need for a precisely matched reference potential or a dummy ferroelectric capacitor. The described method applies a uniform reference potential to both the bit line BL and plate line PL in
FIG. 6
, then floats the bit line while manipulating the plate-line potential in a way that decreases the positive or negative polarization of the ferroelectric capacitor CFe without changing the sign of the polarization. Finally, the plate line PL is returned to the reference potential and the potential of the bit line BL is compared with the reference potential. Depending on the sign of the polarization of the ferroelectric capacitor CFe, the bit-line potential will be higher or lower than the reference potential.
To enable the ferroelectric memory cell in
FIG. 6
to be read by this prior-art method, the bit-line driver BLDu includes a pre-charger PREu and a switch circuit SW. When the switch circuit SW is turned on, the pre-charger PREu drives the bit line BL to a ground potential Vee (=0 V), then to the reference potential Vref. The plate-line driver PLDu drives the plate line PL to a power-supply potential Vcc, the above potentials Vee and Vref, and potentials denoted Vh and Vinv that are respectively higher and lower than Vref. The control circuit CTLu controls the operations of the bit-line driver BLDu, plate-line driver PLDu, selection transistor SLTr, and sense amplifier SA, thereby controlling the storing and reading of information in the ferroelectric memory cell.
FIG. 7
is a timing diagram illustrating the reading of data from the ferroelectric memory cell in
FIG. 6
by the above method of the prior art.
FIG. 8A
is a graph illustrating the polarization of the ferroelectric capacitor CFe during the reading operation in
FIG. 7
when ‘0’ information is stored;
FIG. 8B
is a similar graph illustrating the polarization when ‘1’ information is stored.
FIG. 8A
also illustrates a problem in the prior art.
The symbol r
2
in
FIGS. 8A and 8B
indicates the polarization at timings s
2
and s
3
in FIG.
7
. The symbols r
4
, r
5
, and r
6
respectively indicate the polarization at timings s
4
, s
5
, and s
6
. The horizontal axis in
FIGS. 8A and 8B
indicates the voltage VFe across the two terminals TFe
1
, TFe
2
of the ferroelectric capacitor CFe. The vertical axis indicates the degree of positive or negative polarization (+P or −P) of the ferroelectric capacitor CFe; this quantity (expressible in coulombs per square centimeter) is also known as the polarization charge. The outer curves in these drawings are hysteresis curves illustrating transitions that take place when the polarization of the ferroelectric capacitor CFe changes from the positively saturated state to the negatively saturated state and vice versa.
In the reading operation in
FIG. 7
, after the plate line PL and bit line BL have been brought to the reference potential Vref and the word line WL has been driven to couple the first terminal TFe
1
of the ferroelectric capacitor CFe through the selection transistor SLTr to the bit line BL, the bit line BL is placed in an electrically floating state and the potentials Vh, Vinv, and Vref are applied sequentially to the plate line PL at timings s
4
, s
5
, and s
6
, the bit line BL acting as a capacitive load. The diagonal lines in
FIGS. 8A and 8B
are capacitive load lines for potentials of Vh, Vinv, and Vref on the plate line PL.
In
FIGS. 8A and 8B
, it assumed that while storing ‘0’ or ‘1’ information, the ferroelectric capacitor CFe has lost some of its polarization, so the point r
2
representing the polarization state at timings s
2
-s
3
is located inside the saturation hysteresis curves. The prior-art reading operation will be described under this assumption with reference to
FIGS. 6
,
7
,
8
A, and
8
B. The inner curves in
FIGS. 8A and 8B
indicate polarization state transitions that take place during the reading operation.
Timing s
0
: Start of Reading
At timing s
0
, Vee (0 V) is applied to the plate line PL by the plate-line driver PLDu. The switch control line SWE is at the low logic level (L) and the switch circuit SW is turned on, so 0 V is applied to the bit line BL by the pre-charger PREu. The word line WL is at the low logic level and the selection transistor SLTr is turned off, so the first terminal TFe
1
of the ferroelectric capacitor CFe is in a floating state, electrically disconnected from the bit line BL. The sense amplifier enable line SAE is at the low logic level and the sense amplifier SA is in the high-impedance state, electrically disconnected from the bit line BL.
Timings s
1
-s
2
: Both Terminals at Vref
At timing s
1
, Vref is applied to the bit line BL and plate line PL by the plate-line driver PLDu and pre-charger PREu. At timing s
2
, the word line WL is driven to the high logic level (H) and the selection transistor SLTr is turned on. The first terminal TFe
1
of the ferroelectric capacitor CFe is now coupled through the selection transistor SLTr to the bit line BL, so the two terminals of the ferroelectric capacitor CFe are placed identically at the Vref potential. The polarization at these timings (s
2
-s
3
) is indicated by point r
2
in
FIGS. 8A and 8B
. It is assumed that the voltage drop in the selection transistor SLTr is negligible; this assumption is also made in the description below.
Timing s
3
: Bit Line BL in Floating State
At the next timing s
3
, the switch control line SWE is set to the high logic level and the switch circuit SW is turned off. This disconnects the pre-charger PREu from the bit line BL, placing the bit line BL in the floating state. The bit line BL remains in the floating state from timing s
3
to timing s
7
.
Timings s
4
-s
6
: Read Voltage Sequence
Next, while the bit line BL remains floating, the plate line PL is driven to Vh (>Vref) at timing s
4
, Vinv (<Vref) at timing s
5
, and Vref (the same potential as at timing s
2
) at timing s
6
by the plate-line driver PLDu.
Setting the potential VPL of the plate line PL (the potential of the second terminal TFe
2
of the ferroelectric capacitor CFe) to Vh at timing s
4
creates a positive voltage across the terminals of the ferroelectric capacitor CFe. The polarization state shifts from point r
2
to point r
4
, which is disposed at the intersection of the hysteresis characteristic with the capacitive load line for VPL=Vh. The locus of the state transition from point r
2
to point r
4
fol

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