Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2001-04-27
2004-10-19
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S623000, C438S960000
Reexamination Certificate
active
06806161
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application claims priorities of Korea patent Application No. 2000-22737, filed on Apr. 28, 2000, and Korean patent Application No. 2000-78658, filed on Dec. 19, 2000.
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a low dielectric material essential for a next generation semiconductor device having high density and high performance, and particularly to a process for preparing a porous interlayer insulating film having low dielectric constant containing pores having a size of a few nanometers or less.
(b) Description of the Related Art
The semiconductor industry is moving toward increasing device complexity, requiring shrinking geometric dimensions and higher component integration with greater dimensional densities in integrated circuit devices, e.g. memory and logic chips. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch to increase the wiring density. Current leading-edge logic processors have 6-7 levels of high density interconnect, and interconnect line width is scheduled to decrease to 0.1 &mgr;m around the year 2005.
As device dimensions shrink to less than 0.25 &mgr;m, the propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant. The smaller line dimension increases the resistivity of metal wires, and the narrow intermetal spacing increases the capacitance between the metal wires. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits the overall chip performance. Accordingly, in order to prepare a chip having high speed, a conductor having a low resistance and a dielectric material having low dielectric constant should be used. In addition, the use of a low dielectric material can remarkably decrease the power dissipation and crosstalk noise.
Recently, several semiconductor device manufacturers have put test products on the market that show improvement in their performance of 20% or more, using copper wiring with high electric conductivity instead of using the conventional aluminum wiring. Recently they shift to use of new materials that exhibit low dielectric constant performance, for use in interconnects. If the dielectric films between interconnect layers in integrated circuit can make use of these materials, the effect on operating speed will be the same as that which resulted with the switch from aluminum to copper technology. For instant, if the dielectric constant of the dielectric material is changed from 4.0 to about 2.5, IC operating speed will be improved by about 20%.
The interlayer dielectric material used in semiconductor integrated circuit devices is predominantly SiO
2
, which is generally formed using chemical vapor deposition (CVD) or plasma enhanced techniques and has the requisite mechanical and thermal properties to withstand various processing operations associated with semiconductor manufacturing. The relative dielectric constant of a SiO
2
material varies with the conditions under which a dielectric is formed; that of silicon thermal oxidation films, which have the lowest dielectric constant, is of the order of 4.0. Attempts have been made to reduce the dielectric constant by introducing fluorine atoms into an inorganic film deposited by CVD. However, the introduction of fluorine atoms in large amounts decreases the chemical and thermal stability, so the dielectric constant achieved in actual practice is of the order of 3.5. Fluorinated oxides can provide an immediate near-term solution and a shift to new types of insulating materials with sub-3 dielectric constant may be required.
One class of candidate is organic polymers, some of which have a dielectric constant less than 3.0. Incorporating fluorine into such organic polymers is known to further lower the dielectric constant. Most organic polymers do not, however, possess the physico-chemical properties required for on-chip semiconductor insulation, particularly thermal stability and mechanical properties (sufficient to withstand back end of the line fabrication temperatures within the range of 400~450° C.). Few organic polymers are stable at temperatures greater than 450° C. They also have a low glass transition temperature and thus elasticity thereof remarkably decreases at high temperature, and they have a very high linear expansion coefficient. Since temperature rises to up to 450° C. during semiconductor IC integration and packaging processes, the resulting low thermal stability and elasticity and high linear expansion coefficient can deteriorate the reliability of the device.
Recently in order to solve thermal stability problems of organic polymers, the development of organic silicate polymers using a sol-gel process has emerged. In particular, organic SOG (Spin On Glass) has been proposed for use as interlayer dielectrics in which the side chain of an organic component (an alkyl group such as methyl) is bonded to the backbone chain of a siloxane bond. It has a lower dielectric constant, e.g., the range of about 2.7~3.2, than conventional glasses.
The development of interlayer insulating materials having a low dielectric constant of 2.5 or less is necessary for developing devices of high performance and high density of the next generation, and in order to do this, the introduction of air having a dielectric constant of 1 into materials having dielectric constant of 3.0 to 2.5 is needed.
Brinker et al., U.S. Pat. No. 4,652,467 present a method of forming porous dielectric films on substrates. The process uses a sol-gel technique for depositing porous films with controlled porosity and pore size, wherein a solution is deposited on a substrate, gelled, and then cross-linked and densified by removing the solvent through evaporation, thereby leaving a porous dielectric. Dielectric formed by this method, generally referred to as xerogels, has pores that are generally interconnected, rather than being isolated cells. Dielectrics are typically 10~50% porous with a permanent film thickness reduction of at least 20% during drying.
Sakamato et al. U.S. Pat. No. 5,103,288 report a method to fabricate low density dielectric films on a substrate containing 50% to 80% porosity. The porous insulating film is typically formed by applying a mixture of an acidic oxide and basic oxide on a substrate, heat-treating to precipitate the basic oxide, and then dissolving out the basic oxide. However dissolving all the basic oxide out of such a dielectric film may be difficult and several of elements described for use in the basic oxide such as sodium and lithium can contaminate electronic devices.
Nguyen et al., Chem. Mater. 1999, 11, 3080~3085 describe a method to fabricate porous organosilicates useful for on-chip insulator applications by using precondensed organic silicate and thermally labile polymers. The process involves spin coating a mixture of the matrix material and the thermally labile polymers followed by thermal curing to initiate vitrification and decomposition of the polymers. The microphase-separated domain is formed during the condensation of the organic silicate. However, since the polymers used to form pores have low compatibility with a matrix resin, phase-separated domain tend to become large, and if the contents of polymers increase, an opaque film will easily form. In addition, it may be difficult to generate very small sized pores due to the use of polymers, and to form pores of a uniform size due to the distribution of molecular weight.
Mikoshiba et al., J. Mat. Chem., 1999, 9, 591~598, describe the preparation of porous films containing angstrom size pores. Copolymers comprising methyl(trisiloxysilyl) units and alkyl(trisiloxysilyl) units are spin-coated and cured at 250° C. to provide rigid organic polysilicates. Then films are heated up to 450 or 500° C. to remove thermally labile alkyl groups and pores are formed corresponding to the sizes of the substituents. Trifluoropropyl, cyanoe
Kang Jung-Won
Ko Min-Jin
Moon Myung-Sun
Nam Hye-Yeong
Shin Dong-Seok
Fish & Richardson
Fourson George
LG Chem Investment Ltd.
Pham Thanh V
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