Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt inhibiting or masking
Reexamination Certificate
2002-03-01
2004-11-23
Ray, Gopal C. (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt inhibiting or masking
C710S260000, C709S241000, C712S036000
Reexamination Certificate
active
06823414
ABSTRACT:
TECHNICAL FIELD
Embodiments of the present invention relate generally to apparatus and methods used for program interrupt processing. More particularly, embodiments of the present invention relate to reducing the time required to respond to program interrupts, especially multiple interrupts in rapid succession.
BACKGROUND INFORMATION
A computer system typically includes one or more peripheral devices, such as, for example, a printer, disk drive, keyboard, video monitor, and/or a network interface card (NIC). Most peripheral devices coupled to a computer system generate an electrical signal, or interrupt, when they need some form of attention from a Central Processing Unit (CPU) or processor. This interrupt is usually an asynchronous event that suspends the normal processing operations of the CPU. For instance, a network controller might interrupt to indicate reception of a new packet, or to indicate the successful transmission of an outgoing packet.
Legacy devices generate interrupts by asserting an “interrupt line”, which alerts the host processor to the interrupt. Newer devices may use a Message-Signaled Interrupt (MSI) instead, which makes use of the interrupting device to write a predetermined value (i.e., a message) to a predetermined address in host memory. For example, a network controller might write a special “packet received” message to memory upon receipt of an incoming packet. The MSI message value and address are typically unique to each device.
Computer architecture often makes use of a bus, such as the Peripheral Component Interconnect (PCI) bus, as a mechanism peripheral devices forming various parts of a computer system can use to communicate with each other. Further information on the operation of the PCI bus can be obtained by referring to the PCI Local Bus Specification, Version 2.2, Dec. 18, 1998, published at http://www.pcisig.com. However, most buses are shared, in the sense that more than one peripheral device, such as a network adapter, may reside on the bus at the same time. Thus, when more than one device attempts to communicate with another device on the bus, arbitration occurs, and the bus is granted to only one device at a time. Devices that are prevented from using the bus during this time must wait for the next arbitration cycle to obtain access.
Every access by a device residing on the bus constitutes a “transaction”. Thus, each request to use the bus, arbitration, and grant to use the bus results in a separate transaction. Therefore, if the number of hardware access requests can be reduced, the efficiency of the bus can be increased.
This is quite apparent when there are multiple, high-speed network adapters communicating over a PCI bus. For example, since each adapter has to compete for bus access and participate in the arbitration process in order to process data within the computer system. Typically, each event that occurs in the context of network adapter operation is marked by an interrupt. To process the interrupts, the operating system calls an Interrupt Service Routine (ISR), which reads one or more registers in memory to discover the cause of the interrupt, usually logged in a hardware register called the “interrupt cause register”, which is cleared upon being read, acknowledging the interrupt. Next, the ISR typically disables further interrupts from the interrupting device so that the currently-interrupting event can be processed in an unbroken fashion (i.e., without further interrupts from the same device that diverts CPU processing attention before the ISR has completed its function).
To disable further interrupts, an interrupt “mask” is usually written into a register called the “interrupt mask register”. However, each access to the interrupt mask register typically constitutes a write operation across the bus. Thus, to increase the efficiency of bus operations, there is a need in the art for interrupt processing apparatus and systems, and methods of processing interrupts, which operate to reduce the number of bus transactions due to interrupting events.
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Ray Gopal C.
Schwegman Lundberg Woessner & Kluth P.A.
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