Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-08-01
2004-03-30
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S650000, C438S686000, C438S687000
Reexamination Certificate
active
06713373
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention pertains to methods for fabricating conductive metal line structures on semiconductor devices. It also pertains to certain metal line structures themselves.
Damascene processes for forming integrated circuit metallization layers employ electroplated copper lines formed in vias and trenches of supporting dielectric layers. Copper atoms are rather mobile and can easily diffuse or migrate into the supporting dielectric and thereby reduce its resistance. To address this problem, Damascene processes employ thin diffusion barrier layers on the entire exposed surface of the dielectric. These barrier layers are made from a material that effectively blocks transport of copper atoms into the adjacent dielectric. Typical barrier layers include refractory metal nitrides such as titanium nitride, tungsten nitride, and tantalum nitride, or sometimes oxides such as ruthenium oxide. These layers are sometimes doped with silicon, carbon, boron, and/or oxygen to increase their diffusion barrier properties.
These diffusion barrier materials are not sufficiently conductive to support direct electroplating of copper from solution. So in a Damascene process one first deposits a thin copper seed layer over the entire exposed diffusion barrier layer. This layer is typically formed by physical vapor deposition (PVD) and has a thickness of approximately 100 to 1,000 angstroms. Onto the seed layer, using the Damascene process one deposits a bulk layer of copper by electroplating. Electroplating fills all vias and trenches and continues until copper covers all exposed dielectric. Finally, the excess copper is removed by chemical mechanical polishing (CMP) to provide a planar surface of exposed copper lines encased by dielectric and diffusion barriers.
As device geometries shrink, the use of physical vapor deposited seed layers becomes less attractive because PVD is a non-conformal process. As such, PVD preferentially deposits copper at the top of a trench or via structure. When the vias and trenches have very narrow openings, a non-conformal deposition can cause the top region of the via or trench to close off before the lower levels completely fill with copper. The result is an unacceptable void space in the deposited copper.
FIG. 1
is a schematic side view of a structure
101
produced by the prior art. A Damascene feature
103
is etched into a dielectric layer
105
. A barrier layer
107
is formed over a surface of the dielectric layer
105
. A non-conformal copper seed layer
109
is formed over the barrier layer. Such non-conformal seed layers in small diameter features may form a “pinch off” region
111
, which may create a void. Although the “pinch off” region
111
, as shown, has a slight gap, subsequent deposition of copper may close the “pinch off” region before the part of the feature below the “pinch off” region is filled, creating the void.
Therefore, future generations of device manufacture will likely rely on conformal seed deposition processes such as electroless plating and/or chemical vapor deposition (CVD). Unfortunately, despite considerable effort, it has proved difficult to obtain good adhesion of electroless or CVD copper to typical barrier metals. Further, CVD and electroless films exhibit high contact resistance caused by impurities formed at the interface between the barrier and the copper. This high contact resistance will adversely affect the reliability and performance of the device.
One approach to the problem uses a very thin PVD layer of copper, to provide good adhesion, followed by a thin CVD layer of copper to complete the seed layer. This process still uses PVD. It would be desirable to find a suitable process that employs no PVD copper seed layers.
U.S. Pat. No. 6,365,502 B1, entitled “Microelectronic Interconnect Material with Adhesion Promotion Layer and Fabrication Method”, issued Apr. 2, 2002, teaches the use of CVD deposited cobalt or ruthenium to provide an adhesion region on which copper may be deposited by CVD. The adhesion region promotes the adhesion of the CVD copper.
SUMMARY OF THE INVENTION
To achieve the foregoing and in accordance with the purpose of the present invention, a method of conductive copper lines in a semiconductor device is provided. A dielectric structure having a surface with recessed features formed therein is provided. A ruthenium oxide layer is deposited over the surface of the dielectric structure. A bilayer of ruthenium oxide and metallic ruthenium is formed. Copper conductive lines are formed in the recessed features.
In another embodiment of the invention, a structure formed on a semiconductor substrate is provided. A dielectric structure having recessed features is provided. A conformal layer of ruthenium oxide following contours of the recessed features is provided. A layer of metallic ruthenium intimately contacting the conformal layer of ruthenium oxide is provided. A copper layer filling the recessed features is provided.
In another embodiment of the invention, a method of forming conductive copper lines in a semiconductor device is provided. A dielectric structure having a surface with recessed features formed therein is provided. A diffusion barrier layer is formed over the surface of the dielectric structure. A glue layer comprising at least one of metallic cobalt, ruthenium, and iridium is formed. A copper seed layer is conformally deposited on the glue layer by electroless deposition or atomic layer deposition. Copper conductive lines are deposited in the recessed features such that the copper conductive lines are separated from the dielectric structure by at least the diffusion barrier layer and the glue layer.
In another embodiment of the invention, a method of forming conductive copper lines in a semiconductor device is provided. A dielectric structure having a surface with recessed features formed therein is provided. A metal oxide layer is formed over the surface of the dielectric structure. An exposed portion of the metal oxide layer is reduced to a metal to thereby form a bilayer of metal oxide and metal. Copper conductive lines are formed in the recessed features such that the copper conductive lines are separated from the dielectric structure by at least the bilayer of metal oxide and metal.
The detailed description below will further discuss the benefits and features of this invention.
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Beyer Weaver & Thomas LLP
Fourson George
García Joannie Adelle
Novellus Systems Inc.
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