Method and system for synchronously transferring data...

Details Method and system for synchronously transferring data... Method and system for synchronously transferring data...

2000-12-11

2004-09-14

Lee, Thomas (Department: 2185)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S401000, C713S501000

Reexamination Certificate

active

06792554

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to circuit design and operation of circuits. More particularly, the present invention relates to synchronously transferring control signals in a clock distribution flow. Still more particularly, the present invention relates to transferring data between two different clock domains which are both derived from the same clocking source.
2. Description of Related Art
The clock signal for all memory storage elements on an electronic chip are generated centrally on the chip at the phase locked loop (PLL) and distributed to the memory storage elements through a series connection of wires and buffering circuits. These wires and buffering circuits present a delay element in the clock distribution path. The electrical wire delay is due to the natural parasitic inductive, resistive, and capacitive characteristics of the wire. The buffering circuit delay is generated by the devices within the buffering circuit. As the frequency of the chip is increased, the delay between the launch of a clock edge at the PLL and its arrival at the memory storage elements, can exceed the clock signal time period.
In order to stop the clock for either power dissipation control or debug control, a logic gate is introduced into the clock distribution path in series with the clock distribution wires, buffering circuits and PLL so that the clock signal distributed to the memory storage elements can be forced by the logic gate to either a logic ‘1’ or logic ‘0’ state for an indefinite period of time. The memory storage elements receiving the clock signal generate the control signal for this logic gate, which enables the logic gate to start or stop the clock signal.
It is important for the logic control signal, from the memory storage element, to arrive at the logic control gate while the clock signal logic level is at the desired stop or start logic level so as not to produce an improperly formed clock pulse. The arrival time of the logic control signal from the memory storage element is directly controlled by the delay of the clock distribution path. As that path delay varies, so will the logic control signal arrival time vary at the logic gate potentially causing incomplete clock pulses.
For example,
FIGS. 1A-1D
are exemplary illustrations of a typical clock distribution on a typical electronic chip. Electronic chips may contain logic and memory circuits as well as circuits to support these logic and memory circuits.
FIG. 1
may consist of one or more electronic chips containing logic and memory circuits as well as circuits to support these logic and memory circuits. The logic and memory circuits may be interconnected in a manner to provide the expected operation of a processor, adapter, bridge or interface element (not shown). Located on these one or more electronic chips is a support circuit consisting of serially connected buffers and electrical wires which distribute a periodic clock signal from a centrally generated source to the memory circuits distributed throughout the electronic chip shown as circuit
100
in FIG.
1
A.
In this example, PLL
102
provides clock signal
104
which is distributed throughout the electronic chip using buffering circuits and control circuits
106
,
110
,
114
,
118
,
124
,
128
, and
132
and interconnecting signals
108
,
112
,
116
,
120
,
126
,
130
, C
1
134
, and C
2
136
to memory storage circuit
144
. PLL output signal
104
provides a clock signal input to buffer circuit
106
which may consist of one or more series connected inverter circuits. Buffer circuit
106
may be an inverting or a logically non-inverting circuit. Buffer circuit
106
outputs clock signal
108
which is input to selector circuit
110
. Selector circuit
110
may choose either signal
108
or signal
142
to output signal
112
. For example, if selector signal
148
is at a logic low level (“0”), then selector circuit
110
outputs signal
112
based on clock signal
108
. Otherwise, if selector signal
148
is a logic high level (“1”), then selector circuit
110
outputs signal
112
based on selector signal
142
. In this example, selector signal
148
represents a logic low level (“0”). In other words, output signal
112
becomes the logical value of either clock signal
108
or signal
142
depending on the logical value of selector signal
148
. If selector signal
148
is a logical low level, then output signal
112
is the logically equivalent to clock signal
108
. If selector signal
148
is a logic high level, then output signal
112
is the logical equivalent of signal
142
.
Signal
112
is input to buffer circuit
114
which outputs signal
116
. Signal
116
is input to buffer circuit
118
and outputs signal
120
. Signal
120
is input to buffer circuit
124
which outputs signal
126
. Signal
126
is input to buffer circuit
128
which outputs signal
130
. Buffer circuits
114
,
118
,
124
and
128
may be logically inverting or non-inverting circuits. Signal
130
is input to clock regenerator circuit
132
which outputs signals C
1
134
and C
2
136
to memory storage circuit
144
. Memory storage circuit
144
consists of memory circuit
150
and memory circuit
152
. Memory circuit
150
provides its stored signal
154
to memory circuit
152
. Memory circuit
152
outputs signal
148
.
Clock regenerator circuit
132
outputs signal C
1
134
to memory circuit
150
and provides signal C
2
136
to memory circuit
152
. Clock regenerator circuit
132
provides a buffered logical inversion of signal
130
to output C
1
134
and provides a buffered logical equivalent of signal
130
to output C
2
136
. Signal
158
provides input to memory storage circuit
144
which is transmitted to signal
148
through a sequential process controlled by C
1
134
and C
2
136
.
Signal
158
provides input to memory circuit
150
. When signal C
1
134
is a logical high level (“1”), memory circuit
150
outputs the logical value of signal
158
to stored signal
154
, which is transmitted to memory circuit
152
. When signal C
1
134
changes from a logical high level (“1”) to a logical low level (“0”), the logical value of signal
158
is stored in memory circuit
150
and outputs stored signal
154
to memory circuit
152
. When C
2
136
changes from a logical low level (“0”) to a logical high level (“1”), memory circuit
152
outputs signal
154
to signal
148
. When C
2
136
changes from a logical high level (“1”) to a logical low level (“0”), signal
154
is stored in memory circuit
152
and outputs signal
148
based on stored signal
154
.
Further detailed description of memory storage circuit
144
and similar memory storage circuits may be found in, for example, E. B. Eichelberger and T. W. Williams, “A Logic Design Structure for LSI Testability”, IEEE proceedings of 14th Design Automation Conference, June, 1977, pp. 462-468 and Stephen H. Unger and Chung-Jen Tan, “Clocking Schemes for High-Speed Digital Systems”, IEEE Transactions on Computers, Vol C-35, No. 10, October 1986, pp. 180 to 195. Other similar clock distribution examples may be found in, for example, “Circuits, Interconnections, and Packaging for VLSI”, by Bakoglu, 1990, and IEEE Journal of Solid-State Circuits, Vol 30, No. 4, April 1995, “A Wide-Bandwidth Low-Voltage PLL for PowerPC™ Microprocessors”, by Jose Alvarez, et al, pg. 383, Section VII. In addition, PLL circuits are common in the industry and their functionality on a typical electronic chip for clock signal generation is described in, for example, IEEE Journal of Solid-State Circuits, Vol 27, No. 11, November 1992, “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors”, by Ian A. Young, et al, pg. 1599.
In the present description of the preferred embodiments, a logical high level may be considered a “1”, and a logical low level will be considered a “0”. The memory circuit
150
is considered the “master”, memory circuit
152
is considered the “slave” and memory storage circuit
144
is considered a master/slave flip-flop.
FIGS. 1B
,
1
C, and
1
D

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