Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2003-03-17

2004-12-07

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C365S149000, C365S189050

Reexamination Certificate

active

06828612

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to s semiconductor memory device, and more particularly to a technique effectively applied to a semiconductor memory device such as a DRAM etc. adopting a connection method, which is called a two cells/bit method employing a so-called one-intersection cell.
According to examinations by the inventors of the present invention, the following techniques are available for the DRAM as an example of the semiconductor memory device.
For example, with respect to the DRAM, there are an open bit-line method and a folded bit-line method as methods of connecting a sense amplifier and a bit-line pair. The former open bit-line method is one in which two bit lines to be connected to one sense amplifier are separately connected on both sides to put the sense amplifier therebetween. By the open bit-line method, a so-called one-intersection memory cell structure is formed in which memory cells MC are connected to all of the intersections between the bit-line pair BL and /BL and a word line WL. The theoretical minimum cell area of the one-intersection memory cell is 4F
2
(2F×2F) in terms of a memory-cell-area representing method employing the value “F” of half the pitch of the word line. As a typical example of the one-intersection memory cell, the one having an area of about 6F
2
(2F×3F) has been reported in the academic conference. The latter folded bit-line method is one in which two bit lines to be connected to one sense amplifier are folded and connected in the same direction relative to the sense amplifier. In the folded bit-line method, a so-called two-intersection memory cell structure is formed in which the memory cells MC are connected to half of the intersections between the bit-line pair BL and /BL and the word line WL. The theoretical minimum cell area of the two-intersection memory cell is 8F
2
(4F×2F) in terms of the memory-cell-area representing method employing the value “F” of half the pitch of the word line.
The former open bit-line method has a high risk of obtaining error information from the memory cell since the fluctuation in a word line potential is applied to only one of the bit-line pair due to parasitic capacitance applied between the word line and the bit line. In contrast to this, the latter folded bit-line method can cancel the noise between the bit lines since the fluctuation in a word line potential (noise) is equally applied to both of the bit-line pair via the parasitic capacitance applied between the word line and the bit line. Consequently, the folded bit-line method is one suitable for the DRAM that detects and amplifies the voltage of small signal from the memory cell and, for example, is more frequently used in the DRAM of 64 kbit or lager.
Meanwhile, in DRAM employing the connection method called a two cells/bit method, there is a connection method generally called a two-intersection cell·two cells/bit method among the connection methods of the memory cells arranged at the intersections between the word lines and the bit lines. This two-intersection cell·two cells/bit method has a structure in which: a first memory cell is connected to the intersection between one of the bit-line pair and a first word line; a second memory cell is connected to the intersection between the other of the bit-line pair and a second word line; and the two memory cells correspond to one bit.
Additionally, a memory cell of the one-intersection cell·two cells/bit method is also proposed similarly. This one-intersection cell·two cells/bit method has a structure in which: a first memory cell is connected to the intersection between one of the bit-line pair and a word line; a second memory cell is connected to the intersection between the other of the bit-line pair and the same word line; and the two memory cells correspond to one bit.
Note that as techniques concerning the above-mentioned DRAM employing the one-intersection cell·two cells/bit method, there are recited, for example, Japanese Patent Laid-Open Nos. 61-34790, 55-157194, 8-222706 (U.S. Pat. No. 5,661,678 corresponding thereto), and 2001-143463 (U.S. Pat. No. 6,344,990 corresponding thereto) and Japanese Patent Publication No. 54-28252 (GB patent No. 1,502,334 corresponding thereto), etc. Also, as a technique concerning the DRAM of the two-intersection cell·two cells/bit method, Japanese Patent Laid-Open No. 7-130172 is disclosed.
SUMMARY OF THE INVENTION
Meanwhile, as a result of examination by the inventors about the techniques for the DRAM as described above, the followings have been found.
For example, in a one cell-bit method, since the signal amount on a “H” side is decreased depending on a refresh period, a bit-line signal amount before the amplification of the bit line cannot be used in a high-speed reading method that is read out by a direct sense method. Also, since the one-intersection cell method of the one cell/bit must employ the open bit-line method, array noises become a problem, whereby a reduction in the signal amount is an object to be solved.
As a premise of the present invention examined by the inventors, the two cells/bit method employing the above-mentioned
8
F
2
(4F×2F) will be described with reference to
FIGS. 22 and 23
.
FIG. 22
is a connection diagram showing the state of the connections between the bit-line pairs orthogonal to the word lines and the sense amplifiers.
FIGS. 23A and 23B
are a schematic plan view and a schematic sectional view which show a twin cell structure of the memory cell, respectively.
In the two cells/bit method employing the 8F
2
(4F×2F), the connections between the bit-line pairs orthogonal to the word lines and the sense amplifiers are shown in
FIG. 22
, wherein bit lines BL and /BL are not adjacent to each other and alternately arranged and these two lines are connected to a sense amplifier SA as a bit-line pair BL and /BL. There are a plurality of bit-line pairs BL and /BL connected in this manner, and the sense amplifiers SA are alternately connected to and arranged on the right and left ends of each bit-line pair. Further, each memory cell MC is arranged at positions corresponding to half the ones of the intersections between the bit-line pair BL and /BL and the word line WL.
The two cells/bit method employing the 8F
2
(4F×2F) is, as shown in
FIG. 23A
, constituted to include: a plurality of folded-type bit-line pairs BL and /BL arranged in parallel to each other; a plurality of word lines WL orthogonal to the plurality of bit-line pairs BL and /BL; memory cells MC arranged at position corresponding to half the ones of the intersections between the respective bit-line pairs BL and /BL and the respective word lines WL; and the like. Also, active regions AA on the silicon substrate, in which the source, channel and drain of the transistor of the memory cell MC are formed, are formed in parallel to the bit-line pairs BL and /BL. Note that a portion corresponding to one cell of the memory cell MC is shown by the dash lines.
Further, in the sectional structure thereof, as shown in
FIG. 23B
, the transistor of the memory cell MC is formed on the active region AA in a P well PWEL of the silicon substrate, wherein: a gate electrode is connected to the word line WL; a source electrode is connected via a storage node contact SCT to a storage node SN to be the other of the electrode of the capacitor; and a drain electrode is connected to the bit-line pair BL and /BL via a bit contact BCT. The storage node SN is arranged at the above and opposite point thereof, and constitutes a capacitor between other plurality of capacitors and a plate PL to be one of the electrode common thereto.
Particularly, in the structure of the two cells/bit method employing the 8F
2
(4F×2F), when the half pitch of the word line WL is defined as F, the pitch of the bit-line pair BL and /BL is 2F and that of the word line WL is 2F. Since one memory cell is formed with the pitch equivalent to that of the two word lines WL, the area of one cell of the memory cell is 8F
2
and that of two ce

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3272415