Logic circuit and full adder using the same

Details Logic circuit and full adder using the same Logic circuit and full adder using the same

2000-12-01

2004-03-02

Tran, Anh (Department: 2819)

Electronic digital logic circuitry

Exclusive function

Half-adder or quarter-adder

C326S054000, C326S055000

Reexamination Certificate

active

06700405

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a logic circuit in a semiconductor integrated circuit, more particularly relates to a logic circuit for generating an exclusive-OR (EXOR=A(+)B) and a dual signal thereof (EXNOR=A{circumflex over ( )}(+)B) at almost the same time, and a full adder using the same.
2. Description of the Related Art
8tr Type EXOR and EXNOR Logic Circuits
Conventionally, and also at present, the circuit shown in
FIG. 1
has been generally frequently used as an EXOR logic circuit, and the circuit shown in
FIG. 2
has been generally frequently used as an EXNOR logic circuit (refer to for example John P. Uyemura, “CMOS LOGIC CIRCUIT DESIGN”, Kluwer Academic Publishers, 1999, pp. 274 to pp. 275, FIG. 6.21 to 6.22).
An EXOR logic circuit
1
of
FIG. 1
comprises two CMOS transmission gates TMG
11
and TMG
12
and two CMOS inverters INV
11
and INV
12
and is configured by eight transistors in total.
In this EXOR logic circuit
1
, an input terminal TIN
11
of a logic signal A is connected to an input terminal of an inverter INV
11
, a gate of a p-channel MOS (PMOS) transistor of the transmission gate TMG
11
, and a gate of an n-channel MOS (NMOS) transistor of the transmission gate TMG
12
.
An output terminal of the inverter INV
11
is connected to a gate of the NMOS transistor of the transmission gate TMG
11
and a gate of the PMOS transistor of the transmission gate TMG
12
.
Further, an input terminal TIN
12
of a logic signal B is connected to an input terminal of the inverter INV
12
and one input/output terminal of the transmission gate TMG
11
, while an output terminal of the inverter INV
12
is connected to one input/output terminal of the transmission gate TMG
12
.
The other input/output terminals of the transmission gates TMG
11
and TMG
12
are commonly connected to an output terminal TOT
11
of an exclusive-OR A(+)B.
Similarly, an EXNOR logic circuit
2
of
FIG. 2
comprises two CMOS transmission gates TMG
21
and TMG
22
and two CMOS inverters INV
21
and INV
22
and is configured by eight transistors in total.
In this EXOR logic circuit
2
, an input terminal TIN
21
of the logic signal A is connected to the input terminal of an inverter INV
21
, a gate of the PMOS transistor of the transmission gate TMG
21
, and a gate of the NMOS transistor of the transmission gate TMG
22
.
An output terminal of the inverter INV
21
is connected to a gate of the NMOS transistor of the transmission gate TMG
21
and a gate of the PMOS transistor of the transmission gate TMG
22
.
Further, an input terminal TIN
22
of the logic signal B is connected to an input terminal of the inverter INV
22
and one input/output terminal of the transmission gate TMG
22
, while an output terminal of the inverter INV
22
is connected to one input/output terminal of the transmission gate TMG
21
.
The other input/output terminals of the transmission gates TMG
21
and TMG
22
are commonly connected to an output terminal TOT
21
of a dual signal A{circumflex over ( )}(+)B of the exclusive-OR A(+)B.
6tr Type EXOR and EXNOR Logic Circuits
Further, as an improvement of the 8tr type, there are 6tr type EXOR and EXNOR logic circuits as shown in FIG.
3
and
FIG. 4
(refer to for example John P. Uyemura, “CMOS LOGIC CIRCUIT DESIGN”, Kluwer Academic Publishers, 1999, pp. 275, FIG. 6.23).
The 6tr type EXOR circuit
3
shown in
FIG. 3
comprises a PMOS transistor PT
31
, an NMOS transistor NT
31
, a transmission gate TMG
31
, and an inverter INV
31
and is configured by six transistors in total.
An input terminal TIN
31
of the logic signal A is connected to the gates of the PMOS transistor PT
31
and the NMOS transistor TN
31
and one input/output terminal of the transmission gate TMG
31
.
An input terminal TIN
32
of the logic signal B is connected to a source of the PMOS transistor PT
31
and an input terminal of the inverter INV
31
, while an output terminal of the inverter INV
31
is connected to a source of the NMOS transistor NT
31
.
The drains of the PMOS transistor PT
31
and the NMOS transistor NT
31
and the other input/output terminal of the transmission gate TMG
31
are commonly connected to an output terminal TOT
31
of the exclusive-OR A(+)B.
Similarly, the 6tr type EXNOR circuit
4
shown in
FIG. 4
comprises a PMOS transistor PT
41
, an NMOS transistor NT
41
, a transmission gate TMG
41
, and an inverter INV
41
and is configured by six transistors in total.
An input terminal TIN
41
of the logic signal A is connected to the gates of the PMOS transistor PT
41
and the NMOS transistor TN
41
and one input/output terminal of the transmission gate TMG
41
.
An input terminal TIN
42
of the logic signal B is connected to a source of the NMOS transistor NT
41
and an input terminal of the inverter INV
41
, while an output terminal of the inverter INV
41
is connected to a source of the PMOS transistor PT
41
.
The drains of the PMOS transistor PT
41
and the NMOS transistor NT
41
and the other input/output terminal of the transmission gate TMG
41
are commonly connected to an output terminal TOT
41
of the dual signal A{circumflex over ( )}(+)B of the exclusive-OR A(+)B.
These 6tr type EXOR logic circuit
3
and EXNOR logic circuit
4
are decreased in the number of transistors by two from the 8tr type logic circuits shown in FIG.
1
and FIG.
2
and are excellent in the points of area efficiency and power consumption in comparison with those of the 8tr type.
4tr Type EXOR and EXNOR Logic Circuits
Further, there are 4tr type EXOR and EXNOR logic circuits configured by four transistors as shown in FIG.
5
and
FIG. 6
(refer to for example John P. Uyemura, “CMOS LOGIC CIRCUIT DESIGN”, Kluwer Academic Publishers, 1999, pp. 256, FIG. 5.79).
The 4tr type EXOR circuit
5
shown in
FIG. 5
comprises PMOS transistors PT
51
and PT
52
and NMOS transistors NT
51
and NT
52
and is configured by four transistors in total.
The PMOS transistor PT
51
is connected between an input terminal TINS
1
of the logic signal A and an output terminal TOT
51
of the exclusive-OR A(+)B, while the PMOS transistor PT
52
is connected between an input terminal TIN
52
of the logic signal B and the output terminal TOT
51
.
Further, the NMOS transistors NT
51
and NT
52
are connected in series between the output terminal TOT
51
and a ground GND.
The gate of the PMOS transistor PT
52
and the gate of the NMOS transistor NT
51
are connected to the input terminal TIN
51
, while the gate of the PMOS transistor PT
51
and the gate of the NMOS transistor NT
52
are connected to the input terminal TIN
52
.
Similarly, the 4tr type EXNOR circuit
6
shown in
FIG. 6
comprises PMOS transistors PT
61
and PT
62
and NMOS transistors NT
61
and NT
62
and is configured by four transistors in total.
The NMOS transistor NT
61
is connected between an input terminal TIN
61
of the logic signal A and an output terminal TOT
61
of the dual signal A{circumflex over ( )}(+)B of the exclusive-OR A(+)B, while the NMOS transistor NT
62
is connected between an input terminal TIN
62
of the logic signal B and the output terminal TOT
61
.
Further, the PMOS transistors PT
61
and PT
62
are connected in series between a supply line of a power supply voltage V
DD
and the output terminal TOT
61
.
The gate of the PMOS transistor PT
62
and the gate of the NMOS transistor NT
62
are connected to the input terminal TIN
61
, while the gate of the PMOS transistor PT
61
and the gate of the NMOS transistor NT
61
are connected to the input terminal TIN
62
.
As one element circuit frequently used in a processor in an integrated circuit, there is a full adder.
FIG. 7
is a circuit diagram of an example of the configuration of a generation circuit of a carry signal CO of a full adder.
This carry signal generation circuit
7
is configured by an EXOR logic circuit
71
, transmission gates TMG
71
and TMG
72
, and an inverter INV
71
.
An input terminal TIN
71
of the logic signal A is connected to one input terminal of the

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