Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-24
2004-08-17
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S346000, C257S347000, C257S348000, C257S349000, C257S354000, C257S356000, C257S374000
Reexamination Certificate
active
06777751
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an insulated gate field effect transistor (which will be herein referred to as a “IGFET”) and a semiconductor device using the IGFET.
FIGS. 8A and 8B
are cross-sectional and plan views illustrating the structure of a known IGFET, respectively.
FIG. 8A
illustrates a cross section of the known IGFET taken along the line X—X of FIG.
8
B.
As shown in
FIGS. 8A and 8B
, the known IGFET
500
is formed using an SOI substrate and includes a semiconductor layer
51
, a buried insulating film
52
, and a semiconductor layer
53
serving as an active region. Furthermore, a trench
52
t
is provided so as to surround the semiconductor layer
53
, and the trench
52
t
is filled with an insulating film, thereby forming an isolation region
54
. On a region of the semiconductor layer
53
which is to be a channel, formed are a gate insulating film
55
and a gate electrode
56
in this order. A gate sidewall spacer
57
is then formed so as to surround the gate electrode
56
. Furthermore, an interlevel insulating film
58
is formed on the substrate and then a contact
59
is formed so as to be connected to the gate electrode
56
through the interlevel insulating film
58
. The gate width W1 of the semiconductor layer
53
is about 1 &mgr;m. The interlevel insulating film
58
is not shown in FIG.
8
B.
Next, a method for fabricating the known IGFET
500
will be described with reference to
FIGS. 9A through 9D
.
FIGS. 9A through 9D
are cross-sectional views illustrating respective process steps for fabricating the known IGEFT
500
.
First, in the process step shown in
FIG. 9A
, an SOI substrate including a semiconductor layer
51
, a buried insulating film
52
and a semiconductor layer
53
is prepared. Next, a multilayer film including a silicon oxide film
60
and a silicon nitride film
61
is formed on the SOI substrate and the multilayer film is patterned. Etching is then performed using the patterned multilayer film as a mask to obtain the semiconductor layer
53
serving as an active region and a trench
52
t
to which part of the buried insulating film
52
is exposed.
Next, in the process step shown in
FIG. 9B
, side parts of the semiconductor layer
53
are subjected to preliminary oxidation, thereby forming a side oxide film
62
(having a thickness of about 10 to 30 nm) on the side parts of the semiconductor layer
53
. During the preliminary oxidation, an oxidizing agent enters into the interface between the buried insulating film
52
and the semiconductor layer
53
to oxidize the bottom part of the semiconductor layer
53
simultaneously with the side parts of the semiconductor layer
53
. As a result, a birds' beak-shaped bottom oxide film
62
a
is formed. With the bottom oxide film
62
a
, the peripheral portion of the semiconductor layer
53
is lifted as shown in
FIG. 9B
, and therefore, the semiconductor layer
53
has a shape in which a depression is made in the center portion thereof (which will be herein referred to as a “wing shape”).
Next, in the process step shown in
FIG. 9C
, an oxide film is deposited using CVD on the part of the buried insulating film
52
which is exposed to the trench
52
t
. Subsequently, the upper surface of the substrate is planarized by CMP, and an isolation region
54
is formed. Next, a gate insulating film
55
and a gate electrode
56
are formed and then a gate sidewall spacer
57
is formed. Thereafter, ions of an impurity are implanted using the gate electrode
56
and the gate sidewall spacer
57
as a mask, thereby forming source/drain regions (not shown in FIG.
9
C).
Next, in the process step shown in
FIG. 9D
, an interlevel insulating film
58
is formed by CVD and then a contact
59
is formed so as to pass through the interlevel insulating film
58
and reach the gate electrode
56
.
In the above method for fabricating an IGFET
500
, the peripheral portion of the semiconductor layer
53
is lifted, so that the semiconductor layer
53
becomes to have a wing shape as shown in FIG.
9
B. This lift is caused by the fact that the gate width W1 of the semiconductor layer
53
is about 1 &mgr;m whereas the bottom oxide film
62
a
formed by thermal oxidation extends inwardly from each edge of the semiconductor layer
53
only by a distance of about 0.3 &mgr;m. As a result, a crystal strain occurs in the peripheral portion of the semiconductor layer
53
serving as an active region, thus resulting in crystal defects or abnormal diffusion of a dopant impurity in the semiconductor layer
53
.
In an IGFET, therefore, leakage of a dopant impurity between the drain and the source due to abnormal diffusion of the dopant impurity of the source region and the drain region, junction leakage between the drain and the substrate, or the like easily occurs. Such leakage causes high fraction defective in the IGFET, resulting in a remarkable reduction in the yield of a semiconductor device using the IGFET.
SUMMARY OF THE INVENTION
The present invention has been devised in order to solve the above-described problems, and it is therefore an object of the present invention to provide a semiconductor device of low fraction defective.
A semiconductor device in accordance with the present invention includes: an insulating layer; a semiconductor region formed on the insulating layer; a trench that surrounds side parts of the semiconductor region and reaches the insulating layer; an isolation insulating film formed in the trench; a semiconductor element in which the semiconductor region serves as an active region; a side oxide film formed by oxidizing the side parts of the semiconductor region and located between the rest of the semiconductor region and the isolation insulating film; and a bottom oxide film that is formed by oxidizing a bottom part of the semiconductor region, is located over the entire interface between the rest of the semiconductor region and the insulating layer, and has side surfaces reaching the side oxide film.
As described above, the semiconductor device of the present invention includes a bottom oxide film that is formed by oxidizing a bottom part of the semiconductor region, is located over the entire interface between the rest of the semiconductor region and the insulating layer, and has side surfaces reaching the side oxide film. This suppressed the occurrence of crystal defects or abnormal diffusion of a dopant impurity in the semiconductor region. Therefore, in the semiconductor element in which the semiconductor region serves as an active region, the occurrence of crystal defects or abnormal diffusion of a dopant impurity can be suppressed.
The semiconductor element may be a FET including a gate insulating film formed on the semiconductor region, a gate electrode formed on the gate insulating film, and source/drain regions formed on both sides of the gate electrode.
The semiconductor region preferably has a length of 0.5 &mgr;m or less in the gate width direction.
Another semiconductor device in accordance with the present invention includes: an insulating layer; a semiconductor region formed on the insulating layer; a trench that surrounds side parts of the semiconductor region and reaches the insulating layer; an isolation insulating film formed in the trench; a gate insulating film formed on the semiconductor region; a gate electrode formed on the gate insulating film; a side oxide film formed by oxidizing the side parts of the semiconductor region and located between the rest of the semiconductor region and the isolation insulating film; and a bottom oxide film that is formed by oxidizing a peripheral portion of a bottom part of the semiconductor region, is located under the peripheral portion of the rest of semiconductor and between the rest of the semiconductor region and the insulating layer, and has side surfaces reaching the side oxide film. In the semiconductor device, the semiconductor region has a length of 2 &mgr;m or more in the gate width direction.
Thus, it is possible to reduce the area ratio of part of the semiconductor re
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Ortiz Edgardo
Wilson Allan R.
LandOfFree
Semiconductor device and method for fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method for fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3269862